Switchable PLL circuit with constant amplification gradient

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375223, 375327, 375371, 375373, 375375, H04B 138, H03D 318, H03D 324, H04L 700

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active

055374484

ABSTRACT:
An improved Phase-Locked Loop (PLL) radio receiver circuit includes a phase detector, either an active loop filter or a set of parallel, alternately selectable loop filters, and a Voltage-Controlled Oscillator (VCO) whose input is connected to the output of the loop filter. The output of the VCO is fed to frequency divider. The output of the frequency divider and a reference frequency signal form the inputs to the phase detector/comparator. Toggling among the loop filters occurs such that the loop limit frequency, defined by a loop amplification of 1, is altered by this toggling without significantly changing the gradient of the amplification to the frequency, in a frequency range which includes the limit frequency.

REFERENCES:
patent: 4608699 (1986-08-01), Batlivala
patent: 4862513 (1989-08-01), Bragas
patent: 4888564 (1989-12-01), Ishigaki
patent: 4926447 (1990-05-01), Corsetto
patent: 4929917 (1990-05-01), Yokogawa
patent: 5315623 (1994-05-01), Kuo
patent: 5319680 (1994-06-01), Port
patent: 5341405 (1994-08-01), Mallard
European Broadcasting Union Technical Standard 3244-E, entitled Specifications of the Radio Data System (RDS) for VHF/FM Sound Broadcasting (EBU Technical Centre, Brussels, Mar. '84), pp. 29-30 & table of contents.

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