Switch/network adapter port for clustered computers...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting

Reexamination Certificate

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C710S002000, C710S062000, C709S250000, C716S030000

Reexamination Certificate

active

10996016

ABSTRACT:
A switch
etwork adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

REFERENCES:
patent: 4763294 (1988-08-01), Fong
patent: 4783730 (1988-11-01), Fischer
patent: 4972457 (1990-11-01), O'Sullivan
patent: 5230057 (1993-07-01), Shido et al.
patent: 5265218 (1993-11-01), Testa et al.
patent: 5295246 (1994-03-01), Bischoff et al.
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5673204 (1997-09-01), Klingelhofer
patent: 5737766 (1998-04-01), Tan
patent: 5802290 (1998-09-01), Casselman
patent: 5857109 (1999-01-01), Taylor
patent: 5889959 (1999-03-01), Whittaker et al.
patent: 5892962 (1999-04-01), Cloutier
patent: 5903771 (1999-05-01), Sgro et al.
patent: 5911778 (1999-06-01), Garnett
patent: 5915104 (1999-06-01), Miller
patent: 5923682 (1999-07-01), Seyyedy et al.
patent: 5953502 (1999-09-01), Helbig, Sr.
patent: 5966534 (1999-10-01), Cooke et al.
patent: 5978862 (1999-11-01), Kou et al.
patent: 6023755 (2000-02-01), Casselman
patent: 6026478 (2000-02-01), Dowling et al.
patent: 6038431 (2000-03-01), Fukutani et al.
patent: 6047343 (2000-04-01), Olarig et al.
patent: 6052134 (2000-04-01), Foster
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6094532 (2000-07-01), Acton et al.
patent: 6108730 (2000-08-01), Dell et al.
patent: 6148356 (2000-11-01), Archer et al.
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6202111 (2001-03-01), Wallach et al.
patent: 6295571 (2001-09-01), Scardamalia et al.
patent: 6326973 (2001-12-01), Behrbaum et al.
patent: 6446192 (2002-09-01), Narasimhan et al.
patent: 6452700 (2002-09-01), Mays, Jr.
patent: 6480014 (2002-11-01), Li et al.
patent: 6577621 (2003-06-01), Balachandran
patent: 6581157 (2003-06-01), Chiles et al.
patent: 6598199 (2003-07-01), Tetrick
patent: 6633945 (2003-10-01), Fu et al.
patent: 6704816 (2004-03-01), Burke
patent: 6721884 (2004-04-01), De Oliveira Kastrup Pereira et al.
patent: 6799252 (2004-09-01), Bauman
patent: 6810121 (2004-10-01), Ikesue
patent: 2001/0010057 (2001-07-01), Yamada
patent: 2004/0030816 (2004-02-01), Knight et al.
patent: 0 571 099 (1993-11-01), None
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://cag-www.lcs.mit.edu/raw, Proceedings of the Second SUIF Compiler Workshop, Aug. 21-23, 1997.
Albaharna, Osama, et al., “On the viability of FPGA-based integrated coprocessors”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 206-215.
Amerson, Rick, et al., “Teramac—Configurable Custom Computing”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Video coProcessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Programmable active memories: a performance assessment”, © 1993 Massachusetts Institute of Technology, pp. 88-102.
Bittner, Ray, et al., “Computing kernels implemented with a wormhole RTR CCM”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in a Custom Computing Machine—Chapter 1—Custom Computing Machines: An Introduction”, pp. 1-11, http://www.computer.org/espress/catalog/bp07413/spls-ch1.html (originally believed published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 152-161.
Clark, David, et al., “Supporting FPGA microprocessors through retargetable software tools”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid CM-2/Xilink prototype”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploring architectures for volume visualization on the Teramac custom computer”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al., “Defect tolerance on the Teramac custom computer”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the early 21stcentury”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “Matrix A Reconfigurable Computing Device with Configurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SIMD hybrid and its application to DSP”, © 1992 IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.6.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, © 1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al.,, “Processing in Memory: The Terasys Massively Parallel PIM Array” © Apr. 1995, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Document Relevance with Run-Time Reconfigurable Machines”,© 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiwara, Hiroshi, et al., “A dynamically microprogrammable computer with low-level parallelism”, © 1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al. “A General Approach in System Design Integrating Reconfigurable Accelerators,” http://xputers.informatik.uni-kl.de/papers/paper026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Hartenstein, Reiner, et al., “A reconfigurable data-driven ALU for Xputers”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John, et al.: “GARP: a MIPS processor with a reconfigurable co-processor”, © 1997 IEEE, Publ. No. 0-08186-8159-4/97, pp. 12-21.
Hayes, John, et al., “A microprocessor-based hypercube, supercomputer”, © 1986 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H.—J., et al., “A Reconfigurable Computer for Embedded Control Applications”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., et al., “Enable++: A second generation FPGA processor”, © 1995 IEEE, Publ. No. 0-8186-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an industrial machine vision system”. © 1996 IEEE, Publ. No. 08186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approach to systolic design”, © 1988 IEEE, Publ. No. CH2603-9/88/0000/0463, pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,” ©

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