Switch for bus optimization

Details Switch for bus optimization Switch for bus optimization

2005-01-07

2008-09-16

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S029000

Reexamination Certificate

active

07426602

ABSTRACT:
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

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