Suspend mode operation for reduced power

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Reexamination Certificate

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07853811

ABSTRACT:
An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.

REFERENCES:
patent: 6286107 (2001-09-01), Tamaki et al.
patent: 7026840 (2006-04-01), May et al.
patent: 7295036 (2007-11-01), Zaveri et al.
patent: 7376037 (2008-05-01), Law et al.
patent: 2005/0091629 (2005-04-01), Eisenstadt et al.
Aural Chinnappan and Kathleen Murchek, QuickLogic® Application Note 88, Maximizing Energy Consumptionwith Very Low Power Mode in PolarPro FPGAs Rev. A, Mar. 2006, pp. 1-9.

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