Survivor path memory circuit and Viterbi decoder with the same

Details Survivor path memory circuit and Viterbi decoder with the same Survivor path memory circuit and Viterbi decoder with the same

2006-10-10

2006-10-10

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07120855

ABSTRACT:
A survivor path memory circuit and a Viterbi decoder with the circuit for saving the memory amounts. The Viterbi decoder includes a branch metric generator, an ACS (Add-Compare-Select) unit, a survivor path memory circuit and a decoding unit. The survivor path memory circuit includes survivor paths and decision bit paths. Each survivor path has multiplexers connected in series and each multiplexer outputs the selected data to next multiplexer and to another multiplexers of another survivor paths. Each decision bit path has register node connected in series, receives a decision bit signal generated from the ACS unit, and outputs delayed signal to the multiplexers of the corresponding survivor path. The data flow direction for the survivor paths is opposite to the data flow direction for the decision bit paths. Because the registers in the survivor paths are replaced by the registers in the decision bit paths, the survivor path memory circuit uses less memory, if the number of the decision bit paths is smaller than the number of the survivor paths.

REFERENCES:
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patent: 2002/0094057 (2002-07-01), Shibuya
patent: 2002/0174402 (2002-11-01), Yamamoto

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