Survivor memory device in viterbi decoder using trace deletion m

Details Survivor memory device in viterbi decoder using trace deletion m Survivor memory device in viterbi decoder using trace deletion m

1997-02-28

1998-08-18

Baker, Stephen M.

Excavating

H03M 1312

Patent

active

057967563

ABSTRACT:
A survivor memory device in a Viterbi decoder determines a final survivor path using a trellis diagram and decision vectors, and outputs decoded data corresponding to the determined survivor path. The survivor memory device includes a path existence information generator for receiving a plurality of decision vectors, and for generating first branch path existence information representing whether a branch path exists between each state and the corresponding next states in the trellis diagram. A plurality of units are serially connected with respect to the outputs of the path existence information generator. Each unit comprises a path existence information store for receiving and storing the first branch path existence information, a path removal signal generator for generating corresponding path removal signals when the first branch path existence information corresponding to each current state represents that corresponding branch paths do not exist between each current state and the corresponding next states, and a path existence information updator for receiving the first branch path existence information stored in the path existence information store and the path removal signals generated by the path removal signal generator, and for updating values of second branch path existence information corresponding to each current state to represent that corresponding branch paths do not exist between each current state and the corresponding previous states.

REFERENCES:
patent: 5280489 (1994-01-01), Fredrickson et al.
patent: 5537424 (1996-07-01), Karabed et al.
Fettweis, G., "Algebraic Survivor Memory Management for Viterbi Detectors", SUPERCOMM/ICC '92, pp. 339-343, Dec. 1992.
Black, P. et al., "Hybrid Survivor Path Architectures for Biterbi Decorders", ICASSP '93, pp. I-433 -I-436, Dec. 1993.
Chern, S-J. et al., "A VLSI Architecture of SMU for Strongly Connected Viterbi Decoder", APCCAS '94, pp. 200-205, Dec. 1994.
"A New Survivor Memory Management Method in Veterbi Decoders", IEEE Globecom 1996 Conference Record vol. 1, pp. 126-130.

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