Surface stabilization of silicon rich silica glass using...

Details Surface stabilization of silicon rich silica glass using... Surface stabilization of silicon rich silica glass using...

2000-08-31

2002-04-16

Chen, Bret (Department: 1762)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C427S578000, C427S579000, C427S535000, C438S788000

Reexamination Certificate

active

06372671

ABSTRACT:

This invention relates to the field of semiconductors, and in particular to a method of improving the adhesion of Spin-on-Glass (SOG) films on an underlying dielectric layer.
SOG films are used in very large scale integration (VLSI) circuits for enhanced planarization of the devices. Planarization, as the name implies, involves smoothing out the contours of the underlying layer. Typically, the SOG layer is deposited on an inter-metal dielectric (IMD
1
) layer, which is commonly a PECVD (plasma enhanced chemical vapor deposition) silicon oxide film. A second IMD (IMD
2
) PECVD oxide layer is deposited on the SOG film to cap it and prevent any contact with the upper metallic structures.
In order to obtain a good adhesion between the IMD underlying film and a siloxane-based SOG film, the IMD layer must show strong hydrophilic properties due to the presence of the silanol groups in the SOG layer. Such properties are known to increase and enhance the bonds between the coated SOG film and the PECVD IMD
1
silicon oxide layer. The hydrophilic characteristics can be measured using a goniometer. A goniometer uses the Kaelble technique to obtain the surface tension between a liquid and a solid surface. In this technique, the angle a drop of water makes with the surface is measured. The greater the angle, the less hydrophilic the surface.
When test samples consisting of a SOG film deposited on an IMD
1
film were subjected to temperature cycling tests, severe delamination problems were observed between the SOG layer and the IMD
1
film. Such a test consists of many cycles between ranging between −65° C. and +150° C. The delamination observed at the SOG/IMD
1
interface causes electrical failure of the integrated circuits.
In order to avoid the delamination at the SOG/IMD
1
interface, the adhesion between these films must be enhanced. Any treatment to enhance adhesion should be as simple as possible to avoid forming any cracks in the SOG, which is very delicate. In addition, it should have minimal effect on throughput since additional processing steps increase the cost and complexity of manufacture.
One prior art treatment for improving adhesion, which is described in U.S. Pat. No. 5,556,806, involves treating the IMD
1
layer with an oxygen plasma prior to depositing the SOG. Such a plasma treatment is intended to improve the IMD
1
surface roughness, which it is believed might be helpful in order to enhance the SOG adhesion on IMD
1
. This process, however, involves an extra processing step, which significantly increases the fabrication time, and thus the cost of manufacture of the devices.
According to the present invention there is provided a method of fabricating a semiconductor device, comprising the steps of forming a dielectric layer of silica glass by plasma enhanced chemical vapour deposition (PECVD) wherein a gaseous precursor of said dielectric layer is supplied to a deposition chamber in the presence of an electromagnetic field; discontinuing the supply of said gaseous precursor while continuing to maintain the electromagnetic field for a delay time exceeding 0.5 seconds after the discontinuation of the supply of said gaseous precursor to improve the hydrophilic properties of said film; and depositing a siloxane-based SOG film on said dielectric layer.
This technique has been found to significantly improve the hydrophilic properties of silicon rich silica glass and thus the adhesion to the siloxane-based SOG film. The preferred post time is one second. It can be longer, but should not exceed about 3 seconds since otherwise the dielectric surface will become too rough. It is not believed that it has previously been realized that the post A delay time can affect the hydrophilic properties of the deposited layer.
The dielectric is preferably silicon rich silica glass (SRSG), which is known per se for intermetal dielectic layers (IMD).
As in conventional PECVD, the plasma, normally created by the application of an RF field, activates the reaction between the precursors. The precursors are SiH
4
, N
2
O and N
2
. The N
2
gas is used as a carrier gas in the deposition chamber while the silicon oxide is formed from a reaction between SiH
4
and N
2
O. SiH
4
serves as the source of silicon and N
2
O the source of oxygen.
An important feature of this invention is the fact that the increase in the delay time does not affect the process throughput since no additional ex situ treatments are required. In conventional equipment, the standard delay between the time SiH
4
flow is turned off in the reactor and the RF is turned off (referred to in the art as the post-A delay) is pre-set at 0.5 s. The wafers are then moved to another station for further processing.


REFERENCES:
patent: 4708884 (1987-11-01), Chandross et al.
patent: 5593741 (1997-01-01), Ikeda
patent: 5633208 (1997-05-01), Ishikawa
patent: 5656337 (1997-08-01), Park et al.
patent: 6232216 (2001-05-01), Machida et al.

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