Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2000-09-07
2001-12-25
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S706000, C257S719000, C257S796000, C438S122000
Reexamination Certificate
active
06333551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and structure for coupling a heat sink or heat spreader to a semiconductor chip.
2. Related Art
FIG. 1
illustrates an electronic package
10
with a semiconductor chip
14
coupled to a chip carrier
12
. A heat spreader
16
is coupled to the chip
14
with an interfacing encapsulant
20
between the heat spreader
16
and the chip
14
. If conductive fins
22
are present, then a heat sink comprises a composite of the heat spreader
16
and the conductive fins
22
. Although the discussion infra in this Related Art section discusses only the heat spreader
16
, it should be understood that the heat sink may be present and is analogous to the heat spreader
16
. The encapsulant
20
serves to couple the heat spreader
16
to both the chip
14
and the chip carrier
12
. A layer
21
of the encapsulant
20
between the chip
14
and the heat spreader
16
has a constant thickness (t), wherein t is in a direction that is normal to a surface
15
of the chip
14
. An underfill
18
relieves thermally induced stresses, as well as consequent premature fatigue failure, that might otherwise be imposed on solder connections between the chip
14
and the chip carrier
12
due to differential thermal expansion between the chip
14
and the chip carrier
12
. The differential thermal expansion is a consequence of a coefficient of thermal expansion (CTE) differences between the chip
14
(e.g., 3 to 6 ppm/° C.) and the chip carrier
12
(e.g., 10 to 24 ppm/° C. for an organic chip carrier; 6 to 10 ppm/° C. for a ceramic chip carrier).
The encapsulant
20
typically has a much higher CTE (e.g., 17 to 70 ppm/° C.) than a CTE of the chip
14
(e.g., 3 to 6 ppm/° C.) which causes the encapsulant
20
to swell or contract more
5
than the chip
14
when the electronic structure
10
is heated or cooled, respectively. As the encapsulant
20
swells, the encapsulant
20
expands away from the chip
14
and lifts the heat spreader
16
away from the chip
14
, which causes high thermally induced stresses at the interfaces with both the chip
14
and the heat spreader
16
. Because of the aforementioned thermally induced stresses, the chip
14
or the heat spreader
16
may delaminate from the encapsulant
20
, or a crack in the encapsulant
20
may form and propagate, with an accompanying loss of structural integrity and/or degradation of heat transfer capability. The thermally induced stresses at the interfaces of the chip
14
and the heat spreader
16
to the encapsulant
20
are highest near peripheral edges
24
of the chip
14
.
A method that reduces interfacial thermally induced stresses and does not materially increase thermal resistance is needed for coupling a heat spreader or a heat sink to a chip.
SUMMARY OF THE INVENTION
The present invention provides an electronic package, comprising:
a first structure selected from the group consisting of a semiconductor device and a thermally conductive member;
a second structure, wherein the second structure includes the thermally conductive member if the first structure includes the semiconductor device, and wherein the second structure includes the semiconductor device if the first structure includes the thermally conductive member;
a thermally conductive shape in contact with the first structure; and
a thermally conductive material in contact with the second structure and with the thermally conductive shape, wherein an average thickness of a peripheral portion of the thermally conductive material exceeds an average thickness of a central portion of the thermally conductive material.
The present invention provides a method of forming an electronic package, comprising:
forming a thermally conductive shape on a first structure, wherein the first structure is selected from the group consisting of a semiconductor device and a thermally conductive member;
interfacing a material in an uncured or partially cured state between a second structure and the thermally conductive shape, wherein the material is thermally conductive, wherein the second structure includes the thermally conductive member if the first structure includes the semiconductor device, and wherein the second structure includes the semiconductor device if the first structure includes the thermally conductive member; and
curing the material, wherein an average thickness of a peripheral portion of the cured material exceeds an average thickness of a central portion of the cured material.
The present invention reduces interfacial thermally induced stresses and does not materially increase thermal resistance between the semiconductor device and the thermally conductive member.
REFERENCES:
patent: 4092697 (1978-05-01), Spaight
patent: 4825284 (1989-04-01), Soga et al.
patent: 5510956 (1996-04-01), Suzuki
patent: 6229702 (2001-05-01), Tao et al.
patent: 58111354A2 (1983-07-01), None
patent: 63300519A2 (1988-12-01), None
patent: 6268120A2 (1994-09-01), None
patent: 9115835 (1997-05-01), None
patent: 11163231A2 (1999-06-01), None
Caletka David V.
Johnson Eric A.
Clark Sheila V.
Fraley Lawrence R.
International Business Machines - Corporation
Schmeiser Olsen & Watts
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