Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1999-06-21
2001-12-25
Callahan, Timothy P. (Department: 2816)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S738000, C438S118000, C438S616000
Reexamination Certificate
active
06333564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of producing the same and, more particularly, to a semiconductor device of a surface mount package type and a method of producing the same.
2. Description of the Related Art
Generally, a BGA (Ball Grid Array) type semiconductor device is well known as a semiconductor device of the surface mount package type. The BGA-type semiconductor device has ball-like protrusion electrodes (bumps) as external connecting terminals, and the protrusion electrodes are bonded to a printed circuit board so that the semiconductor device is mounted onto the printed circuit board.
In recent years, there has been an increasing demand for highly reliable electronic equipment onto which semiconductor devices are mounted, and, hence, high reliability is also expected when a semiconductor device is mounted onto a printed circuit board.
FIG. 1
shows a conventional semiconductor device of a surface mount package type. A BGA-type semiconductor device
1
comprises a semiconductor chip
2
, a wiring board
3
(hereinafter referred to as “substrate
3
”), protrusion electrodes
4
(hereinafter referred to as “balls
4
”), and a mold resin
5
. The substrate
3
comprises insulating resin tape
6
made of polyimide (hereinafter referred to as “PI tape”) and a wiring layer
7
. The semiconductor chip
2
is mounted on the upper surface of the substrate
3
with a bonding member
10
.
Ball attachment holes
8
are formed in ball attachment positions in the PI tape
6
of the substrate
3
. The wiring layer
7
is made of copper foil formed into a predetermined pattern. Metal wires
9
are bonded between the wiring layer
7
and the semiconductor chip
2
, and are connected to the balls
4
through the ball attachment holes
8
. In this manner, the semiconductor chip
2
is electrically connected to the balls
4
via the metal wires
9
and the wiring layer
7
.
The balls
4
are bumps which function as external connecting terminals, and are formed by soldering. The balls
4
are bonded to the wiring layer
7
through the ball attachment holes
8
formed in the PI tape
6
. The balls
4
are also disposed on the mounting surface of the substrate
3
(on the bottom surface in
FIG. 1
) in an area array so as to accommodate the high-density semiconductor chip
2
and the small semiconductor device
1
.
The mold resin
5
is formed on the upper surface of the substrate
3
, on which the semiconductor chip
2
is mounted, so as to protect the semiconductor chip
2
, the wiring layer
7
, and the metal wires
9
.
The semiconductor device
1
is surface-mounted on a printed circuit board
11
. More specifically, the balls
4
are positioned with electrodes
12
formed on the printed circuit board
11
, and the semiconductor device
1
is then placed on the printed circuit board
11
. The balls
4
are bonded to the electrode
12
by reflow soldering, so that the semiconductor device
1
is mounted on the printed circuit board
11
.
The semiconductor chip
2
in the semiconductor device
1
generates heat when operated. The temperature of the semiconductor chip
2
rises during when operated, and drops when stopped. By the heat, the semiconductor device
1
thermally expands.
However, since the thermal expansion coefficients of the semiconductor device
1
and the printed circuit board
11
are different, a thermal expansion difference occurs between the semiconductor device
1
and the printed circuit board
11
, thereby causing stress in the bonding position between the semiconductor device
1
and the printed circuit board
11
. Such stress might results in removal of the balls
4
from the electrodes
12
.
To solve this problem, a semiconductor device
20
shown in
FIG. 2
has been developed. In
FIG. 2
, the same components as in the semiconductor device
1
shown in
FIG. 1
are indicated by the same reference numerals.
The semiconductor device
20
is characterized by a buffer member
21
interposed between the semiconductor chip
2
and the substrate
3
. The buffer member
21
is made of elastomer (a low elastic modulus material), and is elastically deformed. The substrate
3
is disposed on the bottom surface (the surface facing the printed circuit board
11
) of the buffer member
21
.
The semiconductor chip
2
has a face-down structure, and the semiconductor chip
2
and the substrate
3
, between which the buffer member
21
is interposed, are electrically connected by the metal wires
9
. A potting resin
22
formed by potting seals the semiconductor chip
2
.
Transfer molding cannot be performed on the structure having the buffer member
21
that can be elastically deformed. For this reason, the potting resin
22
seals the semiconductor chip
2
and the metal wires
9
.
The buffer member
21
interposed between the semiconductor chip
2
and the substrate
3
takes up a thermal expansion difference between the semiconductor device
20
and the printed circuit board
11
. Thus, stress is prevented between the semiconductor chip
2
and the substrate
3
, and the bonding reliability (packaging reliability) between the balls
4
and the electrodes
12
can be improved.
With the semiconductor device
20
, however, there is a problem that the buffer member
21
interposed between the semiconductor chip
2
and the substrate
3
adds to the number of components and complicates the production procedures, resulting in high production costs.
Another problem is that the semiconductor device
20
becomes taller than the semiconductor device
1
by the height of the buffer member
21
between the semiconductor chip
2
and the substrate
3
.
The semiconductor chip
2
attached to the buffer member
21
can be sealed only by the potting resin
22
, and a fillet-like concave portion
23
is inevitably formed on the boundary of the potting resin
22
and the upper surface of the semiconductor chip
2
. Because of the concave portion
23
, the upper surface of the semiconductor device
20
formed by the semiconductor chip
2
and the potting resin
22
is not flat, resulting in another problem that desirable chucking cannot performed with the semiconductor device
20
.
If the semiconductor device
20
is transported using a vacuum chuck, it is necessary to chuck the upper surface of the semiconductor device
20
having the balls
4
formed on the mounting surface (the bottom surface) of the substrate
3
. Especially for the small chip size package shown in
FIG. 2
, it is necessary to vacuum chuck the entire upper surface of the semiconductor device
20
(i.e., the entire upper surface formed by the semiconductor chip
2
and the potting resin
22
).
With the potting resin
22
, however, the upper surface of the semiconductor device
20
is not flat due to the fillet-like concave portion
23
on the upper edge. Furthermore, the entire surface of the vacuum chuck needs to be in contact with the upper surface of the semiconductor device
20
, but air entering through the concave portion
23
lowers the degree of vacuum and hinders secure chucking.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide a semiconductor device and a method of producing the same in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor device which requires lower production costs, is shorter in height, and can be securely chucked.
The above objects of the present invention are achieved by a semiconductor device which comprises: a semiconductor chip; protrusion electrodes which function as external connecting terminals; an interposer which electrically connects the semiconductor chip to the protrusion electrodes; a mold resin which seals at least a part of the semiconductor chip and a part of the interposer; and a connecting portion sealing resin which seals the connecting portion between the interposer and the semiconductor chip. In this semiconductor device, the thermal expansion coefficient of the mold resin is
Abe Mitsuo
Aiba Yoshitaka
Fujisawa Tetsuya
Hamano Toshio
Inoue Hiroshi
Armstrong Westerman Hattori McLeland & Naughton LLP
Callahan Timothy P.
Fujitsu Limited
Nguyen Minh
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