Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-05-21
2004-03-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S535000, C257S665000, C257S734000, C257S780000, C438S215000, C438S613000
Reexamination Certificate
active
06713871
ABSTRACT:
TECHNICAL FIELD
Embodiments of the present invention relate to a surface-mount solder method and apparatus for improved decoupling capacitance.
BACKGROUND INFORMATION
DESCRIPTION OF RELATED ART
Power delivery is a significant concern in the design and operation of a microelectronic device. Where the microelectronic device is a processor or an application-specific integrated circuit (ASIC), an adequate current delivery, a steady voltage, and an acceptable processor transient response are desirable characteristics of the overall microelectronic device package. One of the methods for responding to a processor transient is to place a high-performance capacitor as close to the processor as possible to shorten the transient response time. Although a large-capacity and high-performance capacitor is preferable to answer the processor transients, the capacitor is in competition for space in the immediate vicinity of the processor. This may involve making a cutout in a portion of a board or socket to make room for the capacitor. A cutout in a board is a factor for increasing overall package size, which is counter to the trend to miniaturize. A cutout is also a factor for increasing the loop inductance path for a package, which can have a negative impact on the performance of the microelectronic device.
The loop inductance path is often a convoluted path that complicates the impedance of the package.
FIG. 11
is a depiction of an existing system
10
including a substrate
12
and a top structure
24
that includes an electronic component
26
. A decoupling capacitor
30
is mounted upon the substrate
12
. A convoluted current path
64
can be traced between the capacitor
30
, the electronic component
26
, and back to the capacitor
30
. A convoluted path
64
or convoluted inductance loop is defined as a current that flows in a first pre-component direction
66
and in a substantially reverse, second pre-component direction
68
. “Pre-component” means that the current in this section of the current-convoluted current loop path
64
has not passed, either in whole or in part, through the component
26
, but it has reversed its flow direction. A convoluted path is also defined as a current that flows in a first post-component direction
70
and a substantially reverse, second post-component direction
72
. “Post-component” means that the current in this section of the convoluted current loop path
64
has not passed, either in whole or in party, through the component
26
but it likewise has reversed its flow direction. Such reversal of flow direction creates complicated inductance that is detrimental to performance.
REFERENCES:
patent: 6326677 (2001-12-01), Bloom et al.
patent: 6330164 (2001-12-01), Khandros et al.
Zhao et al., “Effects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages”, Oct. 26, 1998, Sigrity Technical Papers.
Jackson James Daniel
Roth Weston C.
Searls Damion T.
Flynn Nathan J.
Intel Corporation
Wilson Scott R.
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