Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-09-07
2004-09-07
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S111000, C438S127000
Reexamination Certificate
active
06787388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to packaging integrated circuit devices and in particular to providing electrical discharge properties to integrated circuit device packaging. Still more particularly, the present invention relates to forming a metal ring around an integrated circuit from a portion of a lead frame for the purpose of conducting electro-static energy away from the integrated circuit.
2. Description of the Prior Art
In conventional integrated circuits, electrostatic discharge (ESD) events typically enter the circuitry through the pad ring, which dissipates the charge before reaching the core. Some recently developed integrated circuits, however, must necessarily expose the core of the circuitry to ESD events. Contemporary fingerprint sensors, for example, often include a two-dimensional array of sensing electrodes proximate to a sensing surface on which the finger is placed, with ridges and valleys on the finger skin detected by capacitance variations caused by the varying distance between the skin surface and the sensor electrodes. The need for contact with the finger in order to detect fingerprint features necessitates exposure of the integrated circuit to electrostatic discharge events resulting from a finger touching the sensing surface.
The electrostatic charge which may be carried by a human body oftens fall within the range of several kilovolts or more. Typical electrostatic discharge protection circuits have proven somewhat ineffective in safely dissipating such charges, which may provide sufficient energy to break through upper dielectric/passivation layer.
Additionally, integrated circuits which cannot be completely encapsulated—except for conductive leads to the circuit—during packaging (e.g., fingerprint sensors, optical sensors, and other circuit requiring that a portion of the integrated circuit remain exposed) are typically mounted utilizing “Chip On Board” technology. The integrated circuits are mounted on a printed circuit board in an unencapsulated form, connected to the printed circuit board through the bond wires, then protected utilizing liquid encapsulation or silicon gel. Such mounting, which involves the use of gold plating of the substrate, is much more expensive than conventional surface mounting of integrated circuits on a stamped lead frame. However, viable surface mounting of fingerprint sensors on lead frames has not yet been achieved.
It would be desirable, therefore, to provide a technique for surface mounting of fingerprint sensors on lead frames while providing adequate electrostatic discharge protection to the packaged integrated circuit.
SUMMARY OF THE INVENTION
In a packaged integrated circuit, electrostatic discharge protection is provided by portions of a lead frame on which the integrated circuit is mounted. The lead frame includes a die paddle on which an integrated circuit die is mounted, with plastic or epoxy material encapsulating exposed surfaces of the integrated circuit die except for a sensing surface, and supporting pins or leads formed from the lead frame. Portions of the lead frame extending from the die paddle are folded around sides of the encapsulated integrated circuit die and over, or adjacent to and level with, a peripheral upper surface of the encapsulated integrated circuit die to form an electrostatic discharge ring. The lead frame portions folded around the integrated circuit package are connected to ground through a ground pin, so that charge on a human finger touching the electrostatic discharge ring is dissipated to ground before the finger contacts a sensing surface of the integrated circuit. The portions of the lead frame which are folded around the encapsulated integrated circuit die may extend only around sides or side regions of the integrated circuit package not including pins or leads or, alternatively, may extend around all sides of the integrated circuit package and have openings where side regions of the integrated circuit by package includes pins or leads.
REFERENCES:
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patent: 5835988 (1998-11-01), Ishii
patent: 5862248 (1999-01-01), Salatino et al.
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patent: 6165818 (2000-12-01), Ichikawa et al.
patent: 6307258 (2001-10-01), Crane, Jr. et al.
patent: 2002/0027268 (2002-03-01), Tanaka et al.
Coleman W. David
Jorgenson Lisa K.
Munck William A.
Nguyen Khiem
STMicroelectronics Inc.
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