Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2005-02-01
2005-02-01
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S601000
Reexamination Certificate
active
06849480
ABSTRACT:
Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.
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Aw Choon An
Fabry Michael R.
Junge Terry A.
Low Chau Chin
Olson Jonathan E.
Berezny Nema
Berger Derek J.
Jr. Carl Whitehead
Seagate Technology LLC
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