Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1996-10-07
1998-09-15
Niebling, John
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438459, 438667, 438928, 438977, H01L 2176
Patent
active
058077839
ABSTRACT:
A bonded wafer has a first handle wafer 12, a device layer 10', an interconnect layer 14, and a number of vias filled with conductive material that extends between the surfaces 6, 8 of the device layer 10'. the interconnect layer 14 has conductors that connect internal device contacts to the conductive vias. A second handle wafer 40 of glass is bonded to the interconnect layer 14 and the first handle wafer is removed. Bottom, external contacts 36 are formed on surface 6 of device layer 10'.
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Delgado Jose Avelino
Gaul Stephen Joseph
Harris Corporation
Niebling John
Zarneke David
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