Suppression of MOSFET gate leakage current

Details Suppression of MOSFET gate leakage current Suppression of MOSFET gate leakage current

2002-09-17

2004-12-14

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Having diamond semiconductor component

C438S059000, C438S264000, C438S301000, C438S302000

Reexamination Certificate

active

06830953

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of MOSFETs, and more particularly to the selection and method of use of novel materials to suppress gate leakage currents in these devices under various operating conditions as their dimensions are reduced.
2. Description of the Related Art
As the dimensions of MOSFETS (Metal Oxide Semiconductor Field-Effect Transistors) continue to shrink, the reduced length of the channel between source and drain causes unwanted side-effects (short-channel effects) due to the increased electric field intensity therein. One way in which such effects have been addressed is by forming an asymmetric lightly doped drain within the transistor, a method taught by Chien et al. (U.S. Pat. No. 5,510,279). Another way of alleviating these side-effects is by reducing the thickness of the oxide layer between the gate electrode and the semiconductor surface. This suppresses the short channel effects and also allows V
DD
(drain supply voltage) to be reduced while maintaining an acceptable drain current. However, the thin dielectric layer also has disadvantages, most notably allowing power-consuming leakage currents between the gate and the source, drain and channel regions the transistor within the semiconductor. These difficulties are pointed out by S.-H. Lo et al (“Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs,” IEEE Electron Device Letters, Vol. 18, No. 5, May 1997, p. 209). One approach to reducing undesirable gate leakage currents is by forming the channel region in a moat-like shape, with a central region beneath the gate being more heavily doped to create, therein, a high threshold-voltage (V
T
). This method is taught by Houston (U.S. Pat. No. 6,261,886 B1). Another approach to reducing gate leakage currents is the use of dielectric materials with high dielectric constants (high-k dielectrics), such as HfO
2
, Al
2
O
3
and La
2
O
3
. The use of such dielectrics, while producing encouraging results, has proven to be difficult to integrate within present processing methods while still maintaining good channel interface quality and high carrier mobility. A discussion of this high-k dielectric approach is to be found in D. A. Buchanan et al. (“80 nm poly-silicon gated n-FETs with ultra thin Al
2
O
3
gate dielectric for ULSI applications,” IEDM Technical Digest, Washington D.C., Dec. 5-8, 1999, pp. 223-226).
An alternative approach, which is embodied in the present invention, reduces gate leakage currents by gate-material engineering, which is the selection of gate materials (eg. doped semiconductor materials) whose band structures can be matched to the band structures of the source, drain and channel regions of the substrate portions of the transistor so that the tunneling states, required for leakage currents to exist, are made unavailable during various operating conditions of the transistor. This approach can be used to suppress gate leakage currents not only in MOSFETS of standard configuration, but also in SOI (Silicon on Insulator) MOSFETS with single gates or double gates such as are described by X. Huang et al. (“Sub 50-nm FinFet: PMOS” IEDM Technical Digest, Washington D.C., Dec. 5-8, 1999, pp. 67-70). It should also be pointed out that the use of SOI technology, most notably SOS (Silicon on Sapphire) technology has already been applied to the reduction of leakage currents between neighboring device structures (see, in this regard, Mayer et al. (U.S. Pat. No. 4,753,895), but this approach is not applicable to eliminating leakage currents within the device itself, which is the object of the present invention. It should also be noted that the choice of metal gate materials for forming MOS gate terminals, as opposed to Schottky type terminals, is also applied to device fabrications in SiC substrates as taught by Bhatnagar et al. (U.S. Pat. No. 6,146,926), so the method of the present invention would be applicable even in that case.
SUMMARY OF THE INVENTION
The primary object of this invention is to provide a method for significantly reducing gate leakage currents under a variety of operating conditions within a MOSFET having a thin gate dielectric.
In accord with the objects of this invention there is provided a method for significantly reducing source, drain and channel-to-gate leakage currents by effectively eliminating states within the gate electrode and the transistor channel, source and drain regions between which carriers can tunnel. The method involves gate-material engineering, selecting a particular gate electrode material, channel material and dielectric material such that there can be obtained an alignment of their band structures that makes the availability and/or the accessibility of charge-carrier tunneling states energetically extremely difficult or impossible. Thus:
1. When the full supply voltage, V
DD
, is applied to the gate, so that the transistor is under maximum inversion bias, the accumulated carriers in the gate (holes, assuming a p
+
doped semiconductor gate material for an n-channel transistor) will have no accessible states within the channel to allow tunneling.
2. When the full supply voltage, V
DD
, is applied to the gate, so that the transistor is under maximum inversion bias, the carriers (electrons) in the channel will have no tunneling states accessible to them in the gate to allow tunneling.
3. When the full supply voltage, V
DD
, is applied to the gate and zero bias is applied to the source, the accumulation carriers in the source will have no tunneling states available in the gate and/or the accumulation carriers in the gate will have no available tunneling states available in the source (assuming here a p
+
gate and an n
+
source) for leakage currents to be produced in the gate/source overlap region.
4. When the full supply voltage V
DD
is applied to the drain and the gate is at zero bias, both the gate and drain regions in the gate/drain overlap region will be depleted of charge carriers. In this condition the lack of free carriers in the vicinity of the gate dielectric will significantly reduce or eliminate leakage current between the gate and drain in the overlap region.
It will be shown that gate electrodes formed of prior art materials, such as heavily n-doped polysilicon, cannot achieve these objects. The present invention will demonstrate that low electron affinity materials and negative electron affinity materials can achieve these objects.


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