Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-15
2004-11-02
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S751000, C257S754000, C148S033300
Reexamination Certificate
active
06812529
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the suppression of cross diffusion and/or gate depletion in integrated circuit devices. More particularly, the present invention relates to a scheme for suppressing cross diffusion and gate depletion in a 6T SRAM cell.
Integrated circuit devices commonly employ a laminar or polysilicide structure composed of a polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. In many cases, the polycrystalline silicon film comprises an N+ polysilicon region doped with an N type impurity and a P+ polysilicon region doped with a P type impurity. The present inventors have recognized that many P+ and N+ dopant materials are subject to migration from a given polysilicon layer to another polysilicon layer, to an overlying conductive layer, or to another region of the given polysilicon layer. As a result, these opposite types of impurities are subject to cross diffusion. This cross diffusion can lead to performance degradation in the integrated circuit device.
Accordingly, there is a need for a scheme for suppressing cross diffusion of dopant materials between oppositely doped regions of polysilicon layers in integrated circuit devices.
BRIEF SUMMARY OF THE INVENTION
This need is met by the present invention wherein an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride.
In accordance with one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer over the N type active region and a P+ polysilicon layer over the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.
In accordance with another embodiment of the present invention, a memory cell is provide comprising a semiconductor substrate, a P well, an N well, an NMOS transistor, a PMOS transistor, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate. The NMOS transistor defines an N type active region in the P well. The PMOS transistor defining a P type active region in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer forming a portion of the NMOS transistor and a P+ polysilicon layer forming a portion of the PMOS transistor. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.
Preferably, the diffusion barrier layer comprises an ultrathin diffusion barrier layer and has a thickness of between about 5 Å and about 25 Å.
In accordance with yet another embodiment of the present invention, an SRAM memory cell is provided comprising a semiconductor substrate, a P well, an N well, a flip flop, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well formed in the semiconductor substrate. The N well formed is in the semiconductor substrate. The flip-flop is formed by two access transistors and a pair of cross coupled inverters. Each pair of cross-coupled inverters includes a pull up transistor and a pull down transistor. The pull-up transistor defines a P type active region in the N well and the pull-down transistor defines an N type active region in the P well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer forming a portion of the pull-down transistor and a P+ polysilicon layer forming a portion of the pull-up transistor. The diffusion barrier layer is formed in the polysilicide gate electrode structure between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film over a substantial portion of the polycrystalline silicon film.
In accordance with yet another embodiment of the present invention, an SRAM memory cell is provided comprising a semiconductor substrate, a P well, an N well, a flip flop, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The flip-flop is formed by two access transistors and a pair of cross coupled inverters. Each pair of cross-coupled inverters includes a pull up transistor and a pull down transistor. The pull-up transistor defines a P type active region in the N well and the pull-down transistor defines an N type active region in the P well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer forming a portion of the pull-down transistor and a P+ polysilicon layer forming a portion of the pull-up transistor. The diffusion barrier layer is formed in the polysilicide gate electrode structure between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film over a substantial portion of the N+ polysilicon layer and the P+ polysilicon layer.
In accordance with yet another embodiment of the present invention, a memory cell array is provided comprising a plurality of SRAM cells arranged in rows and columns. Each cell of the array is connected to a word line and to a pair of bit lines and comprises a semiconductor substrate, a P well, an N well, a flip flop, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The flip-flop is formed by two access transistors and a pair of cross coupled inverters. Each pair of cross-coupled inverters includes a pull up transistor and a pull down transistor. The pull-up transistor defines a P type active region in the N well and the pull-down transistor defines an N type active region in the P well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer forming a portion of the pull-down transistor and a P+ polysilicon layer forming a portion of the pull-up transistor. The diffusion barrier layer is formed in the polysilicide gate electrode structure between the polycrystalline silicon film
Abbott Todd R.
Cho Chih-Chen
Trivedi John D.
Violette Mike
Wang Zhongze
Dinsmore & Shohl LLP
Fourson George
LandOfFree
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