Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-07
2002-12-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C713S002000, C713S100000, C710S014000, C711S001000, C326S038000, C326S040000, C326S041000, C326S047000
Reexamination Certificate
active
06496971
ABSTRACT:
TECHNICAL FIELD
This invention relates to configuring a memory-based programmable logic device. More particularly, this invention relates to configuring a memory-based field programmable gate array (FPGA).
BACKGROUND INFORMATION
A field programmable gate array (FPGA) is a general purpose programmable device that is customizable by an end user to realize a desired user-specific circuit. The basic device architecture involves an array of configurable logic blocks (CLBs) embedded in a configurable interconnect structure and surrounded by configurable I/O blocks (IOBs). Each IOB is configurable to be an output buffer, an input buffer, or a bidirectional buffer. An IOB is configurable to register incoming data, to register outgoing data, and/or to provide a tri-state output. A CLB is configurable to perform one of many logic functions. For example, a CLB may be configured to realize combinatorial logic elements, sequential logic elements, lookup tables, and/or control multiplexers. To realize a desired user-specific circuit, the end user configures the configurable interconnect structure to connect the circuitry of multiple configured CLBs and multiple configured IOBs together so that the resulting circuit is the desired user-specific circuit.
In one type of FPGA called a memory-based FPGA, the IOBs, the CLBs and the programmable interconnect structure of the FPGA are configured by loading configuration data into associated configuration memory cells. Each IOB and CLB has associated configuration memory cells, the contents of which determine how the IOB or CLB is configured. Similarly, the programmable interconnect structure includes configuration memory cells. The programmable interconnect structure includes programmable points which control connection of wiring segments in the programmable interconnect structure. Each programmable interconnect point may be a pass transistor controlled by an associated configuration memory cell. Wire segments on each side of the pass transistor are either connected or not connected depending on whether the transistor is turned on by the associated configuration memory cell. Further information about FPGAs appears in “The Programmable Logic Data Book 1999”, copyright 1999 by Xilinx, Inc. and available from Xilinx, Inc., at 2100 Logic Drive, San Jose, Calif. 95124 (the subject matter of this data book is incorporated herein by reference).
Configuration is the process of loading configuration data into the configuration memory cells which control the programmable interconnect structure, the IOBs, and the CLBs. An FPGA available from Xilinx, Inc. generally supports more than one configuration mode. In a first configuration mode called the “Master Serial Mode”, configuration data is typically stored in an external memory such as an external ROM. The FPGA uses an on-chip oscillator to emit a clock signal that causes successive bits of the configuration data to be read out onto a data terminal of the external memory. The data terminal of the external memory is coupled to an input terminal of the FPGA (an IOB that is configured to be an input terminal) such that the successive bits of configuration data are read into the FPGA in serial fashion, one bit at a time. The configuration memory cell that each respective configuration data bit is written to is determined by the location of the configuration data bit in the serial stream of configuration data bits. In one mode, the configuration data is broken up into packets of data called frames. As each frame is received, it is shifted into a frame register until the frame register is filled. The configuration data in the frame register is then loaded in parallel into one row of configuration memory cells. The configuration memory cells in this case are organized for loading purposes as a two-dimensional array. Following the loading of the first frame, a subsequent frame of configuration data is shifted into the FPGA, and another row of configuration memory cells is loaded. In this way, configuration data is loaded into the FPGA in serial fashion, one bit at a time, but the two-dimensional array of configuration memory cells is loaded in parallel, one frame at a time.
The loading of the configuration data into the FPGA in serial fashion can be undesirably time consuming. A Xilinx FPGA therefore typically supports a second configuration mode called the “Master Parallel Model”. In this second mode, configuration data is loaded into the FPGA from an external memory (for example, a ROM) in parallel fashion, eight bits at a time. The FPGA outputs a twenty-two bit address onto twenty-two address terminals of the FPGA (twenty-two IOBs used as output terminals). These twenty-two address terminals of the FPGA are coupled to a corresponding twenty-two address terminals of the external ROM. The FPGA increments the address to cause successive eight-bit configuration data values to be read out of the external ROM and into the FPGA on eight data input terminals (eight IOBs used as input terminals). Multiple such eight-bit values of configuration data bits are assembled to form a frame of configuration data. The configuration data bits of this frame are then written in parallel into a row of the two-dimensional array of configuration memory cells. A second frame of configuration bits is then read into the FPGA and is written in parallel form into a second row of the two-dimensional array of configuration memory cells. In this way, configuration data bits are loaded into the FPGA as a series of eight-bit values, and the two-dimensional array of configuration memory cells is loaded one frame at a time.
For backward compatibility purposes, it is generally desired that each successive FPGA family support the configuration modes (called “legacy configuration modes”) supported by prior families. A new configuration mode may also be added to new FPGA families from time to time. Accordingly, more and more hardware has generally been required to support an ever increasing number of “legacy configuration modes”. A solution is desired that reduces the amount of hardware required to support multiple configuration modes.
SUMMARY
Rather than using dedicated hardwired logic to support multiple configuration modes, a processor is provided on the FPGA for this purpose. After power-up, the processor reads a configuration mode code present on predetermined terminals of the FPGA. The configuration mode code read from these terminals determines the configuration mode that will be used to load configuration data into the FPGA.
If the configuration mode code has a first value, then the processor executes a first program. Execution of the first program causes the processor to control IOBs and other hardware on the FPGA so as to load configuration data onto the FPGA and into the configuration memory cells in accordance with a first configuration mode. If, on the other hand, the configuration mode code has a second value, then the processor executes a second program. Execution of the second program causes the processor to control IOBs and other hardware on the FPGA so as to load configuration data onto the FPGA and into the configuration memory cells in accordance with a second configuration mode. The first and second programs executed by the processor may be stored in on-chip metal-mask read-only-memory (ROM) such that a program can be changed without having to re-layout the remainder of the FPGA and without having to incur significant cost. Providing multiple configuration programs executable on the same processor allows the FPGA to support multiple configuration modes using the same processor hardware.
In one embodiment, a new user-provided configuration mode is supported. If the configuration mode code read after power-up has a particular value, then the processor executes a loader program. Execution of the loader program causes the processor to control IOBs on the FPGA such that a user-provided configuration program is read onto the FPGA and is loaded into program memory used by the processor. Such a user-provided configuration program may, for
Lesea Austin H.
Trimberger Stephen M.
Kik Phallaka
Smith Matthew
Wallace T. Lester
Xilinx , Inc.
Young Edel M.
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