Support method for designing a semiconductor device

Details Support method for designing a semiconductor device Support method for designing a semiconductor device

2006-12-11

2009-12-08

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07631285

ABSTRACT:
In a support method of designing a semiconductor device, a plurality of wiring lines are arranged in parallel in a wiring line layer to transfer a same signal. A wiring line inhibition area is set in the wiring line layer to cover a space between the plurality of wiring lines and to inhibit arrangement of another wiring line other than the plurality of wiring lines.

REFERENCES:
patent: 5375069 (1994-12-01), Satoh et al.
patent: 5717600 (1998-02-01), Ishizuka
patent: 6704918 (2004-03-01), Ali et al.
patent: 6714903 (2004-03-01), Chu et al.
patent: 2004/0123262 (2004-06-01), Shirota et al.
patent: 2003-141200 (2003-05-01), None

Affiliated with

Also associated with

Rating

Support method for designing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Support method for designing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Support method for designing a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4143917