Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-03-19
2001-03-06
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S723000, C257S777000
Reexamination Certificate
active
06198136
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to power rail and signal line buffer circuits for communication external to a core complementary metal oxide semiconductor (CMOS) integrated circuit chip. More particularly, it relates to a semiconductor package having buffer circuits located on a support chip adjacent to the core integrated circuit chip.
BACKGROUND OF THE INVENTION
In CMOS technology, electrostatic discharge (ESD) protection circuits are traditionally located at each signal line pad of each integrated circuit chip needing protection. ESD circuits are also sometimes located between the power supply rails of the integrated circuit chip.
Several problems arise from integrating ESD protection circuits at each signal line pad and between power supply rails. First, ESD protection circuits for chips having a large number of signal lines consume about 5 to 8% of chip area. Therefore, present ESD protection practice adds substantially to the cost of each chip. Second, as the size of devices and wiring on integrated circuit chips scales to smaller and smaller dimensions, the integrated circuit chips become more sensitive to ESD: thinner oxides, shallower junctions, narrower wiring, shorter and narrower channels and the drive to reduce parasitic leakages all tend to increase the ESD sensitivity of a chip and drive up the size and complexity of ESD protection circuits. Third, ESD protection devices built in technologies having shallow trench isolation (STI) structures for isolating adjacent active components from one another have higher resistance, and therefore do not work as well as ESD protection devices built in traditional thermally grown isolation technologies (LOCOS). To compensate for this higher resistance the ESD circuits must be made larger, again driving up manufacturing costs. Fourth, ESD protection devices formed on silicon-on-insulator (SOI) chips have been found to provide less ESD protection than ESD devices formed in bulk silicon, significantly increasing the size of ESD protection devices needed on chips having SOI to achieve ESD performance comparable to that available in traditional bulk silicon. And fifth, with each generation of chip fabrication technology, a significant effort is undertaken to reinvent and redesign ESD protection circuits to accommodate the needs of the new technology, adding to its cost and increasing the time needed to bring the new technology to market.
Potential alternatives, such as providing a portion of an SOI chip with bulk devices, add further to cost and process complexity. Further difficulties, such as crystalline defects may also thereby be introduced.
In addition to ESD circuits, other buffer circuits that are integrated at each signal line pad, such as drivers, receivers, and decoupling capacitors, use a significant amount of chip area. Particular difficulties arise in a mixed voltage environment, in which an integrated circuit chip receives or drives signal at a voltage higher than that used to operate the chip. The higher voltage puts chip yield and reliability at risk because of such well known mechanisms as hot electron degradation, dielectric breakdown, latch up, and MOSFET snapback. Circuit designers have addressed these concerns by incorporating more complex drivers and receivers into the chip, but these measures have driven up the area consumed and lowered the operational performance of the chip. Similarly, the possibility of defects in the dielectrics of large decoupling capacitors connected between power rails of high speed CMOS logic chips provides yield and reliability concerns in addition to area concerns.
A better solution is needed that provides future generations of chips with a high level of ESD protection, capable of operating in a mixed voltage environment, and capable of providing a large amount of decoupling capacitance without consuming a significant part of chip area or degrading chip yield or reliability, and this solution is provided by the following invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide ESD protection circuits and other buffer circuits, such as decoupling capacitors, drivers, and receivers, without consuming area on a core integrated circuit chip.
It is a further object of the present invention to provide ESD protection circuits for core integrated circuit chips formed in a technology for which provision of ESD protection circuits is difficult, such as SOI, without adding to process complexity.
It is a further object of the present invention to decouple the technology used for fabricating the core integrated circuit chip from the technology used to fabricate ESD protection circuits and other buffer circuits.
It is a feature of the present invention to provide buffer circuits, such as ESD protection circuits, on a separate elongate support chip adjacent the core integrated circuit chip.
These and other objects of the invention are accomplished by a semiconductor package comprising a carrier having a lead for external contact, a core integrated circuit chip and an elongate support integrated circuit chip. The elongate support chip has a length-to-width ratio of at least 4 and comprises a lead-buffer circuit electrically connected to the core integrated circuit chip and to the lead. The core chip and the support chip can be manufactured in different technologies to minimize cost.
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“Off-Chip Electrostatic Discharege Protection”, IBM TDB 32, 6B, Nov. 1989.
Never James M.
Voldman Steven H.
Crane Sara
International Business Machines - Corporation
Leas James M.
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