Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1997-12-30
2001-10-23
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S324000
Reexamination Certificate
active
06308278
ABSTRACT:
TECHNICAL FIELD
The present invention relates to power conservation within a digital computer, and more particularly, to a power management system for a desktop computer.
BACKGROUND OF THE INVENTION
Reducing the power consumed by a computer has two significant advantages: 1) less power must be supplied to the computer; and 2) less heat must be dissipated by the computer into the surrounding environment. On a warm day, many businesses pay both for the electricity to power their computers and for the electricity for the air conditioning to cool their buildings.
Reducing power consumption in desktop personal computers (PCS) has recently become a priority. In an office environment, personal computers are often left powered up all day, and sometimes 24 hours a day. In part, this is because booting a PC can take several minutes after power is restored until the PC is usable. PCS are also left on due to user inattention to energy conservation. Nevertheless, most PCS are operating usefully only a small percentage of the business day. While one PC consumes a modest amount of power, hundreds or thousands of PCS left on during the day waste a significant amount of energy. Therefore a need exists to reduce power consumption in a PC during inactivity.
FIG. 1
illustrates a block diagram of a typical computer, such as a PC. PC
110
includes a host processor
112
connected to a local bus
114
. Host processor
112
may be, for example, a Pentium® processor available from Intel Corp. for executing instructions and controlling operation of the PC. A dynamic random access memory (DRAM) card
120
and a memory controller
122
are also connected to local bus
114
. A Peripheral Component Interface (PCI) bus
124
is connected to a magnetic hard disk drive (HDD)
134
, a graphics card
136
, and one or more PCI expansion slots
128
. A local bus/PCI bridge
126
operates as an interface or bridge for local bus signals and PCI bus signals. PC
110
also includes an Industry Standard Architecture (ISA) bus
140
. The ISA bus
140
is connected to the PCI bus via a PCI/ISA bridge
132
. One example of a PCI/ISA bridge
140
is the 8237AB PCI-TO-ISA/IDE Xcelerator (PIIX4), available from Intel Corp. The ISA bus is connected to an audio card
144
, one or more ISA expansion slots
138
, and a Super input/output (I/O) chip
146
. The Super I/O chip includes a keyboard and mouse controller, a floppy drive controller, two serial ports, a parallel port, and an infra-red (IR) port. Many PCS use a Super I/O chip
146
to interface various I/O devices in the PC, such as a keyboard and mouse, floppy drives, printers, and the like. One example of the Super I/O chip is the FDC37C67x 100 Pin Enhanced Super I/O Controller With Fast IR, available from Standard Microsystems Corp.
The PIIX4 chip, the Super I/O chip and the system software (the basic input/output system or BIOS and the operating system) can operate to place the computer into a sleep or power saving mode in which power is conserved.
In one power-saving mode for example, a command can be provided to halt the host processor
112
to conserve power. However, in these power-saving modes, the standard operating voltages (3.3V, 5.0V at 10-13 A) are still provided from the power supply to the motherboard and various peripheral components to allow the components to detect activity (e.g., keyboard or mouse movement, LAN activity) and then “wake” the computer to resume normal operation. As a result, a significant amount of power (typically 30-40 Watts) must be supplied from the power supply to the computer during these power saving modes.
When the power supply is plugged in and the external mechanical power switch is not depressed, the power supply typically provides only about 0.1 A of trickle current only to a portion of the PIIX4 chip to allow the PIIX4 chip to detect the depression of the external mechanical power switch. The PIIX4 chip and the system software operate to reestablish normal power and cold boot the computer when the PIIX4 chip detects the depression of the external power switch. However, because power is not applied to any other portion or component of the computer, it is impossible to “wake” the computer from this mechanical Off state. Therefore, a need exists for an improved power management system that allows a peripheral or component to wake the computer from a power saving mode while consuming less power.
SUMMARY OF THE INVENTION
The power management system of the present invention overcomes the disadvantages of the prior art by supplying only a standby voltage to a portion of the computer that may be involved in waking the computer. Computer activity is detected, and then a wake signal is generated in response to the computer activity. The normal voltage is supplied to the computer in response to the wake signal.
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SMC's PC Input/Output Products, Jul. 10, 1997, Standard Microsystems Corporation, pp. 1-4.
SMC's FDC37C67x, 100 Pin Enhanced Super I/O Controller with Fast IR, Jul. 10, 1997, Standard Microsystems Corporation, pp. 1-2.
Bosker, J., & Kienzle, M., Oct. 10, 1997, Fast Infrared Technology for Cordless Connectivity, IBM MicroNews, pp. 1-6.
Mullgrave, Jr., A. Oct. 19, 1997, IBM Chips at 200Mbps Drive 1394 High-Speed Serial Bus, IBM MicroNews, pp. 1-6.
82371AB PCI-To-ISA/IDE Xcelerator (PIIx4), Apr. 1, 1997, Intel Corporation, pp. 1-225.
Advanced Configuration and Power Interface Specification (ACPI), Rev. 1.0, Dec. 22, 1996, pp. 1-1 to 16-260.
Khouli Sami
Mughir Taha
Nelson Albert Rudy
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Lefkowitz Sumati
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