Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-24
2001-09-18
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S355000, C257S371000, C257S544000, C327S143000
Reexamination Certificate
active
06291862
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to a supply voltage reduction circuit.
BACKGROUND OF THE INVENTION
Most integrated circuits are designed to operate using a specific power supply voltage range. For example, a memory device may be designed to operate using a nominal 12 volt supply, and a range of ±5% or ±10%. If the integrated circuit were designed to use an internal voltage less than the supply voltage, the supply voltage is often regulated with internal circuitry to produce the lower voltage level. Certain integrated circuits have different externally supplied voltages for specific functions. For example, a FLASH memory device may receive an externally supplied voltage to program a floating gate memory cell.
The need for higher supply voltages is reduced as integrated circuit process technologies are developed to reduce the size of components, such as transistors. These components cannot handle the such high voltage levels without sustaining damage. For compatibility with prior devices, however, new integrated circuits should be capable of operating at the previous supply voltage levels. To reduce the supply voltage to a level which is desired, a transistor can be coupled to the supply voltage. The transistor, coupled as a diode, is designed to have a breakdown voltage which exceeds the supply voltage level. In an integrated circuit where the components are designed to handle lower voltages, additional process steps and masks are required to fabricate a transistor capable of handling a high voltage. That is, the transistor would require special process considerations, such as a thicker gate oxide and/or a larger gate and/or different source/drain implants.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a voltage reduction circuit which allows a new generation of an integrated circuit to be compatible with voltage levels used in prior generations, while eliminating additional process steps.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. An integrated circuit is described which includes a simple voltage reduction circuit.
In particular, the present invention describes an integrated circuit comprising a substrate, a connection for receiving an externally supplied voltage having a first upper level, and a first input transistor having a drain and gate coupled to the connection for reducing the externally supplied voltage and providing an internal voltage having a second upper level at a source of the first input transistor. The first input transistor is fabricated in a first well structure to isolate the input transistor from the substrate such that the first input transistor has an operational breakdown voltage which is less than the first upper voltage level.
In another embodiment, an integrated circuit voltage reduction circuit comprises an n-well fabricated in an integrated circuit substrate. The n-well has bottom and side walls. The voltage reduction circuit includes a first n-channel transistor having a drain and gate coupled to an external connection for receiving an externally supplied voltage, and a second transistor coupled to the source of the first n-channel transistor. The first n-channel transistor is located within the n-well to isolate the first n-channel transistor from the substrate such that the first n-channel transistor has an operational breakdown voltage which is less than the externally supplied voltage level. The first n-channel transistor also reduces the externally supplied voltage by an n-channel threshold voltage to provide an internal voltage at a source of the first n-channel transistor.
In yet another embodiment, a flash memory device comprises an array of non-volatile memory cells, a connection for receiving an externally supplied signal having a first upper voltage level, a voltage reduction circuit having an input coupled to the connection for converting the externally supplied signal to an internal signal available at an output of the voltage reduction circuit, and an internal circuit coupled to the output of the voltage reduction circuit. The internal signal has a second upper voltage level which is lower than the first upper voltage level. The voltage reduction circuit comprises a first n-channel transistor having a drain and gate coupled to the input of the voltage reduction circuit. The first n-channel transistor is fabricated in an n-well structure and has a source coupled to the output of the voltage reduction circuit.
REFERENCES:
patent: 5581206 (1996-12-01), Chevallier et al.
patent: 5698972 (1997-12-01), Keeth
patent: 6103573 (2000-08-01), Harari et al.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Wojciechowicz Edward
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