Supply enabled optimization output buffer

Details Supply enabled optimization output buffer Supply enabled optimization output buffer

2006-11-21

2006-11-21

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Tri-state

C326S057000, C326S081000, C326S087000

Reexamination Certificate

active

07138830

ABSTRACT:
An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level. A control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level.

REFERENCES:
patent: 4855623 (1989-08-01), Flaherty
patent: 5929668 (1999-07-01), Kim

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