Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-08-26
2002-10-08
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S215000
Reexamination Certificate
active
06463524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates in general to a data processing system and, in particular, to a superscalar processor. Still more particularly, the present invention relates in general to a superscalar processor and method for efficiently executing a store instruction, wherein a part of the store instruction is executed prior to all of the store instruction's operands being available.
2. Description of the Related Art:
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required. These multiple instructions may be executed in their original sequence, or out of order in a sequence which is different in some way from the original sequence.
Such a microprocessor architecture typically utilizes LOAD and STORE instructions to move data between storage locations such as main memory, cache, register locations, and/or other types of storage locations. A LOAD/STORE instruction includes an address of the data to be moved.
LOAD and STORE instructions are first dispatched from a dispatch buffer. They are then stored in one or two slots within an issue queue where they remain until the operands necessary to execute the instructions are available. For example, STORE instructions require two address operands or a single address operand and an immediate addressing value, and a data operand. The STORE instruction is received within the issue queue where it remains until all operands are available. When all the operands are available, including all data and address operands, the issue queue will issue the STORE instruction from the issue queue to a single execution unit for execution. When the instruction is issued, the issue queue slot or slots are then available for storing another instruction.
Therefore, a need exists for a data processing system and method for efficiently executing a store instruction, wherein a part of the store instruction is executed prior to all of the operands necessary to execute the store instruction being available.
SUMMARY OF THE INVENTION
A processor and method are disclosed for efficiently executing a store instruction. The store instruction is stored in an issue queue within the processor. A first part of the store instruction is issued from the issue queue to a first one of different execution units in response to a first operand becoming available. A second part of the store instruction is issued from the issue queue to a second one of the different execution units in response to a second operand becoming available. The store instruction is completed in response to executing the first part of the store instruction by the first one of the execution units and the second part of the store instruction by the second one of the execution units.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5673427 (1997-09-01), Brown et al.
patent: 5896505 (1999-04-01), Shimazaki
patent: 5918034 (1999-06-01), Petolino
patent: 6009513 (1999-12-01), Mahalingaiah et al.
patent: 6061772 (2000-05-01), Webber
patent: 6119075 (2000-09-01), Dean
patent: 6134646 (2000-10-01), Feiste
patent: 6163821 (2000-12-01), Keller
patent: 6189089 (2001-02-01), Walker
Delaney Maureen
Le Hung Qui
McDonald Robert
Nguyen Dung Quoc
Victor David W.
Bracewell & Patterson L.L.P.
Coleman Eric
England Anthony V. S.
International Business Machines - Corporation
LandOfFree
Superscalar processor and method for incrementally issuing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Superscalar processor and method for incrementally issuing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Superscalar processor and method for incrementally issuing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2967323