Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1997-09-25
1999-10-19
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing control
Branching
G06F 942
Patent
active
059681691
ABSTRACT:
A return stack is described which stores return addresses associated with subroutine call instructions along with an ESP register value associated with the subroutine call instructions in a stack-type structure. During clock cycles that a return instruction is detected by a decode unit, the decode unit forwards an ESP register value associated with the return instruction to the return stack along with an indication of the return instruction detection. The return stack compares the forwarded ESP register value to the ESP register value stored on the top of the stack. If the values compare equal, then the value stored on the top of the stack may be the correct prediction address for this return instruction and is popped from the top of the stack. When the return stack detects an inequality between the two aforementioned ESP values, the return stack does not pop the top of the stack. The return stack may achieve a correct prediction rate substantially similar to the correct prediction rate in the absence of fake return instructions, even if fake return instructions are encountered.
REFERENCES:
patent: 5136697 (1992-08-01), Johnson
patent: 5179673 (1993-01-01), Steely, Jr. et al.
patent: 5222220 (1993-06-01), Mehta
patent: 5274817 (1993-12-01), Stahl
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5355459 (1994-10-01), Matsuo et al.
patent: 5454087 (1995-09-01), Narita et al.
patent: 5526498 (1996-06-01), Matsuo et al.
patent: 5564118 (1996-10-01), Steely, Jr. et al.
patent: 5574871 (1996-11-01), Hoyt et al.
patent: 5584001 (1996-12-01), Hoyt et al.
patent: 5606682 (1997-02-01), McGarity
patent: 5649225 (1997-07-01), White et al.
patent: 5655098 (1997-08-01), Witt et al.
Foreign Search Report dated Feb. 26, 1997 for PCT/US96/11842.
Tomasula, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, Jan. 1967, pp. 25-33.
Dialog, Microprocessor Report, Oct. 24, 1994, pp. 1-7.
IBM Technical Disclosure Bulletin, "Subroutine Call/Return Stack," Apr. 30, 1988, vol. 30, No.11, pp. 221-225.
IBM Technical Disclosure Bulletin, "Highly Accurate Subroutine Stack Prediction Mechanism," Mar. 10, 1986, vol. 28, No. 10, pp. 4635-4637.
Yeh and Patt, "Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue Superscalar Processors," Dept. of Electrical Engineering, University of Michigan, An Arbor, 1993, pp. 164-175.
IBM Technical Disclosure Bulletin entitled, "Highly Accurate Subroutine Stack Prediction Mechanism," vol. 28, No. 10, Mar. 1986, Armonk, US, pp. 4635-4637, XP000616841.
IBM Technical Disclosure Bulletin entitled, "Subroutine Call/Return Stack," vol. 30, No. 11, Apr. 1, 1988, pp. 221-225, XP000097388.
International Search Report for PCT/US 96/11842 dated Feb. 26, 1997.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Kivlin B. Noel
Merkel Lawrence J.
Patel Gautam R.
LandOfFree
Superscalar microprocessor stack structure for judging validity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Superscalar microprocessor stack structure for judging validity , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Superscalar microprocessor stack structure for judging validity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2050081