Superposed quadrature modulated baseband signal processor

Details Superposed quadrature modulated baseband signal processor Superposed quadrature modulated baseband signal processor

1984-06-12

1987-02-17

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 39, 375 61, 332 37R, H04B 1500

Patent

active

046445650

ABSTRACT:
A signal processor for providing a continuous raised cosine output signal having no jitter or intersymbol-interference and with controllable main and side lobes. An NRZ input signal is converted to a double interval raised cosine pulse signal having an amplitude normalized to 1.0. Another single interval raised cosine pulse signal having a peak amplitude (A-1) is superposed with the former raised cosine pulse to provide the output signal.

REFERENCES:
patent: 3048784 (1962-08-01), Scherer
patent: 3377625 (1968-04-01), Filipowsky
patent: 3605017 (1971-09-01), Chertok et al.
patent: 3634773 (1972-01-01), Kobayashi
patent: 4159526 (1979-06-01), Mosley, Jr. et al.
patent: 4176248 (1979-11-01), Sheets
patent: 4261053 (1981-04-01), Dostis et al.

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