System and method for modelling integrated circuit bridging faul

Details System and method for modelling integrated circuit bridging faul System and method for modelling integrated circuit bridging faul

1994-10-13

1997-09-23

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364578, G06F 1750

Patent

active

056711506

ABSTRACT:
A system and method for simulating bridging faults uses means for retrieving, as a function of voltage, strengths of simple transistor circuits relative to the strength of a reference device. This relative strength is used to determine the voltage at bridge faults. The bridge voltage is compared to the threshold voltages of devices connected to the bridging node to determine the logic interpretation by such gates of such voltage. Other systems and methods are disclosed.

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Renovell et al., "A Unified Model for Inter-Gate and Intra-Gate CMOS Bridging Fault: The Configuration Ration," IEEE, 1994, pp. 170-175.
Chess et al., "On Evaluating Competing Bridge Fault Models for CMOS ICS", IEEE, 1994, pp. 446-451.
Millman et al., "Special Application of The Voting Model for Bridging Faults," IEEE, 1994, pp. 263-270.

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