Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-04
2004-07-27
Le, Vu A. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S213000, C257S141000, C257S341000, C257S347000, C257S493000
Reexamination Certificate
active
06768180
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to a superjunction lateral double diffused metal oxide semiconductor field effect transistor (SJ-LDMOST) device fabricated on an insulator substrate. More specifically, the invention provides a device having improved on-state, off-state, and switching characteristics of lateral power devices for power integrated circuits applications.
BACKGROUND OF THE INVENTION
The performance of power integrated circuits (PICs) relies heavily on the on-state and off-state characteristics of a family of lateral power metal oxide semiconductor field effect transistors (MOSFETs), termed lateral double diffused MOSFETs (LDMOSTs), that utilize the reduced surface field technique (RESURF) to achieve high breakdown voltage while maintaining low on-resistance. For a detailed description of RESURF lateral device technology refer to J. A. Appels and H. M. J. Vaes, “High Voltage Thin Layer Devices (RESURF Devices)”, IEEE International Electron Device Meeting (IEDM), Dig. Tech Papers, pp. 238-241, 1979; incorporated herein by reference. The cross-section of a RESURF LDMOST device
10
implemented in a bulk p− type substrate
12
is shown in FIG.
1
. The device
10
is typically fabricated on a thin epitaxial layer
14
to enhance the vertical depletion of the drift region
16
. The device
10
further includes a source electrode
18
, a drain electrode
20
, a gate electrode
22
, a polysilicon gate
24
, a gate oxide layer
26
, a field oxide layer
28
, an n+ type source contact region
30
, an n+ type drain contact region
32
, and a p+ layer
34
. Electrical isolation between adjacent devices is achieved by junction isolation (JI) where a reverse bias is applied to the p+ layer
34
at the source electrode
18
.
In RESURF LDMOST devices, the specific on-resistance increases with the breakdown voltage due to the increase of the low doped drift region length L
D
. Optimum breakdown voltage is achieved provided that the product of the doping concentration N
D
and the thickness of the epitaxial layer, t
epi
, is in the order of 1 to 2×10
12
cm
−2
(known as the RESURF condition) which puts a limit on the upper bound of the doping concentration in the drift region and hence the minimum achievable specific on-resistance. Nevertheless breakdown voltages up to 1200V have been achieved using the RESURF technique and modifications of the technique such as a double RESURF device
36
structure, which includes a p− region
38
in the surface of the n− drift region
16
, as shown in FIG.
2
. For a detailed description of double RESURF technology, see J. S. Ajit, D. Kinzer and M. Ranjan,” 1200V High-Side Lateral MOSFET in Junction-Isolated Power IC Technology Using Two Field Reduction Layers”, Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 230-235, 1993; incorporated herein by reference.
The RESURF LDMOST may be fabricated on a silicon-on-insulator (SOI) substrate
40
as shown in FIG.
3
. The technology is known as dielectrically isolated (DI) silicon technology. The dielectric isolation is achieved by inserting a buried oxide (BOX) layer
42
between the substrate
44
and the epitaxial layer
46
, while lateral isolation
48
is carried out by either local oxidation of thin silicon films (LOCOS) or by trench etching and refilling the trench with a dielectric. Power devices and low voltage components in a PIC may be implemented in silicon islands that are completely surrounded by a dielectric allowing higher packing density. Other advantages provided by DI silicon technology include reduced leakage currents and low parasitic capacitances.
For RESURF LDMOST in SOI the vertical depletion in the drift region
16
is due to a field effect action through the intermediate BOX layer
42
. The BV in this case is dependent on the charge in the top silicon epitaxial layer
46
as specified by the RESURF condition, the silicon layer thickness under the n+ diffusion, and the BOX thickness. Devices with uniform lateral electric field distribution are realized by using a laterally linear doping profile in the drift region resulting in BV of 860V for a silicon film thickness of 0.2 &mgr;m and a BOX thickness of 4.4 &mgr;m. For a detailed description of this type of device see S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Mukherjee, and H. Pein, “Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness in SOI RESURF LDMOS Transistor”, Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Proceedings, pp. 124-128, 1993; incorporated herein by reference. Higher BV in DI technology requires thicker BOX layers, however, overly thick BOX layers may cause wafer warpage and bending, in addition, the effects of self-heating become more pronounced as the BOX thickness increases due to poor thermal conductivity of the oxide.
In high voltage LDMOSTs, the drift region resistance dominates the total on-resistance of the device. For breakdown voltages over 1200V the specific on-resistance of the LDMOST is impractically large. Therefore for further development of high voltage LDMOSTs, the emphasis has been to reduce the drift region resistance.
The superjunction concept may be applied to Vertical DMOSTs to achieve reduced on-resistance in devices having a high breakdown voltage. Superjunction vertical double diffused MOSFET (SJ-VDMOST) provide reduced resistivity of the drift region in vertical power devices.
The first discrete commercial SJ-VDMOST device
50
, illustrated in
FIG. 4
, was introduced by Deboy et al. and labeled CoolMOS™, which is the trademark of SIEMENS AG, of Munich, Germany. The device
50
includes a source electrode
18
, a drain electrode
20
, a gate electrode
22
, channel regions
52
, and alternatively stacked heavily doped n pillars
54
and p pillars
56
called SJ pillars
58
. For a detailed description of the CoolMOS™ device, see i) G. Deboy, M. Marz, J. P. Stengel, H. Strack, J. Tihanyi and H. Weber, “A New Generation of High Voltage MOSFETs Breaks the Limits Line of Silicon”, Proceedings of International Electron Devices Meeting (IEDM), pp. 683-685, 1998; and ii) L. Lorenz, G. Deboy, A. Knapp and M. Marz, “COOLMOS™—A New Milestone in High Voltage Power MOS”, Proceedings of the 11th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 3-10, 1999; incorporated herein by reference. The CoolMOS™ structure achieves a factor of 5 reduction in the on resistance with respect to a state of the art conventional 600V VDMOST. At the same time the device demonstrates superior switching characteristics.
The CoolMOS™ structure is based on the SJ concept. For a detailed description of the theoretical background work of the SJ concept applied to semiconductor devices, see i) U.S. Pat. No. 4,754,310; ii) U.S. Pat. No. 5,216,275; iii) U.S. Pat. No. 5,438,215; and iv) X. B. Chen, P. A. Mawby, K. Board, C. A. T. Salama, “Theory of a Novel Voltage Sustaining Layer for Power Devices”, Microelectronics Journal, vol. 29, pp. 1005-1011, 1998; incorporated herein by reference. The SJ concept may be explained with the aid of FIG.
5
. The SJ concept is based on achieving charge compensation in the SJ drift region
60
which may be realized by replacing the low doped drift region in a VDMOST with alternatively stacked, heavily doped n pillars
54
and p pillars
56
; SJ pillars
58
. When a reverse bias is applied to the SJ pillars
58
(forward blocking mode), an electric field is established which depletes the SJ pillars
58
of their charge carriers moving them in opposite directions towards their respective ohmic contacts
62
and
64
as shown in FIG.
5
(
a
). The depletion region edges spread out of the SJs
66
(the junctions between the n pillars
54
and p pillars
56
) towards depletion edges extending from neighboring SJs
66
.
During this initial stage of the blocking mode the electric field increases fairly rapidly. Once depletion regions from ad
Nassif Sameh Khalil
Salama C. Andre T.
Le Vu A.
Menz Doug
Rossi & Associates
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