Superconductor device and method of manufacturing the same

Details Superconductor device and method of manufacturing the same Superconductor device and method of manufacturing the same

2005-09-13

2005-09-13

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000

Reexamination Certificate

active

06943453

ABSTRACT:
A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

REFERENCES:
patent: 5734607 (1998-03-01), Sung et al.
patent: 6160297 (2000-12-01), Shimizu et al.
patent: 6411548 (2002-06-01), Sakui et al.
K. Ueno, et al. “A Quarter-Micron Planarized Interconnection Technology With Self-Aligned Plug,” IEDM Tech. Dig., 1992, pp. 305-308.
Kazuyoshi Ueno, et al., “A Half-Micron Pitch Cu Interconnection Technology,” VLSI Tech. Dig., 1995, pp. 27-28.
R.F. Schnabel, et al. “Slotted Vias For Duel Damascence Interconnects in 1Gb DRAMs,” VLSI Tech. Dig., 1999, pp. 43-44.
U.S. Appl. No. 09/470,518, filed Dec. 22, 1999.
U.S. Appl. No. 09/670,990, filed Sep. 26, 2000, allowed.
U.S. Appl. No. 09/726,582, filed Dec. 1, 2000, pending.
U.S. Appl. No. 10/108,574, filed Mar. 29, 2002, pending.

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