Electronic digital logic circuitry – Superconductor – Tunneling device
Reexamination Certificate
2003-04-11
2004-12-28
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Superconductor
Tunneling device
C326S001000, C326S002000, C365S162000
Reexamination Certificate
active
06836141
ABSTRACT:
RELATED APPLICATIONS
This application is related to co-pending application Ser. No. 10/411,106, filed concurrently herewith and entitled “Superconductor Output Amplifier,” the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates generally to superconductor systems and, more particularly, to a superconductor memory array with a simplified architecture and associated high bandwidth transmission line signal propagation.
2. Background of the Invention
Digital superconductor logic circuitry operating at cryogenic temperatures and at high speeds on the order of, for example, 20 GHz, requires compatible superconductor random access memory (RAM) arrays. Such RAM arrays include memory cells, each of which includes a storage loop with a switchable Josephson junction storage element, and each of which is capable of storing binary information based on the presence and direction (clockwise or counterclockwise) of a persistent loop current therein. Ideally, such RAM arrays are dense, have low power requirements and have an associated low latency and high throughput.
While superconductor RAM arrays are known, none meet all of the above criteria. Therefore, superconductor RAM arrays are typically considered as a limiting factor in digital superconductor technology. Specifically, nearly all of conventional superconductor RAM array designs require some type of a sense amplifier in each memory cell to detect changes in the memory cell binary state, such as those changes that occur during READ operations, and to accordingly inform the logic circuitry. These sense amplifiers increase the overall array footprint and increase the array power requirements as well as the latency of signals propagating through the array.
In addition, because each column of memory cells is typically treated as a large parasitic inductance, a voltage READ level must be set and then stabilized over a period of time to compensate for an inductance/resistance (L/R) relaxation time constant representative of signal propagation latency and corresponding power dissipation due to array transmission line impedance mismatch.
In view of the above limitations, it is therefore an object of the present invention to provide a superconductor memory array formed from a high bandwidth transmission line of engineered impedance.
It is also an object of the present invention to provide a superconductor RAM array that is dense, has low associated power dissipation and has an associated low latency and high throughput.
It is another object of the present invention to provide a superconductor RAM array that has a simplified architecture in which a sense amplifier is not required for each array cell.
In view of the above, the present invention provides a superconductor memory array with a high associated throughput, low power dissipation and a simple architecture. The superconductor memory array includes memory cells arranged in a row-column format and each including a storage loop with a Josephson junction for storing a binary value. Row address lines each are magnetically coupled in series to a row of the memory cells, and column address lines each are connected in series to a column of the memory cells. A sense amplifier is located on each of the column address lines for sensing state changes in the memory cells located in the columns during a READ operation initiated by row address line READ signals.
According to another embodiment, the present invention provides a superconductor memory cell configuration including memory cells arranged in a column, each of the memory cells including a storage loop with a Josephson junction for storing a binary value. A column address line connects the memory cells in series, and a sense amplifier located on the column address line senses state changes in the memory cells during a READ operation.
According to another embodiment, the present invention provides a superconductor memory configuration with a memory cell including a storage loop with a Josephson junction for storing a binary value, a row address line input magnetically coupled to the storage loop for receiving a READ voltage signal to initiate a READ operation, a column address line input connected to the Josephson junction for receiving a series of SFQ pulses, for outputting all of the series of SFQ pulses if an internal persistent loop current does not change direction during the READ operation, and for outputting fewer than all of the series of SFQ pulses if the internal persistent loop current changes direction during the READ operation, and a bridge resistor arranged in parallel with the Josephson junction for damping the Josephson junction. The superconductor memory configuration also includes a non-dedicated sense amplifier for receiving all of the series of SFQ pulses if the internal persistent loop current does not change direction during the READ operation, for receiving fewer than all of the series of SFQ pulses if the internal persistent loop current changes direction during the READ operation, and for outputting a signal indicative of the binary value stored in the storage loop based on how many of the series of SFQ pulses it receives.
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Northrop Grumman Corporation
Posz & Bethards, PLC
Tran Anh Q.
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