Electronic digital logic circuitry – Superconductor
Reexamination Certificate
2000-11-02
2001-05-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Superconductor
C365S162000, C327S367000
Reexamination Certificate
active
06229332
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to superconductive logic gates and more specifically to superconductive logic gates utilizing Josephson junctions and applications thereof.
Field of the Invention
Superconductive logic gate assemblies are well known. Superconductive logic gate assemblies have been developed using superconductivity quantum interference devices (SQUID) which utilize a parallel combination of two or more Josephson junctions which are connected together by an inductor.
Random access memories based upon superconductive Josephson junctions have been made. These memories require row and column address decoders which are the greatest consumer of power as a result of the decoder being in an active state during memory operation. The decoders which have been used in these superconductive applications are based upon latching logic driven by a microwave frequency clock. The decoders of the most optimized designs for a sizable memory (1 MB) require prohibitive power consumption.
A NOR logic gate assembly using SQUIDs is disclosed in the publication entitled “A 5-32 Bit Decoder for Application in a Crossbar Switch” at pps. 2671-2674, Vol. 3, No. 1, March 1993, IEEE Transactions on Applied Superconductivity. The SQUID NOR gate assembly requires the gate to be reset by turning off the gate current Igate with an AC clock. The resetting of the SQUIDs, which detect memory address signals, must be synchronous with the input data rate of the address signals. The utilization of an AC clock for resetting SQUIDs adds complexity to the design of SQUID based logic circuits. Additionally, AC bias can cause undesired circuit resonances dependent upon the inductance and capacitance of the SQUID as discussed in the aforementioned publication.
U.S. Pat. No. 5,233,244 discloses a Josephson logic gate which utilizes the aforementioned AC bias to reset the individual SQUIDs.
SUMMARY OF THE INVENTION
The present invention is a superconductive logic gate assembly which permits the implementation of various logic functions including, but not limited to, NOR logic. The superconductive logic gate assembly, when configured as an NOR gate, has applications permitting its use in a superconductive random access memory as a row address decoder and column address decoder.
The present invention applies a DC bias to SQUIDs connected in series. The use of a single power lead for applying the DC bias simplifies the topology of an integrated circuit superconductive logic gate assembly in accordance with the present invention by making additional area available for the memory array. At least one damping resistor, which preferably provides critical damping to each SQUID, performs the function of resetting the SQUID to respond to the input of logic levels. Each damping resistor eliminates hysteresis in SQUIDs which latch logic states that in the prior art required an AC bias. The present invention provides asynchronous operation relative to the input data rate with no synchronization being required between the data input rate and resetting of the SQUIDs. The at least one damping resistor coupled across the SQUIDs dissipates stored energy making resetting at a clock rate synchronous with the input data rate unnecessary. Preferably, a damping resistor is coupled in parallel to each of the Josephson junctions of each SQUID.
The present invention operates as a superconductive logic gate assembly at refrigerated temperatures, such as 10EK at which Josephson junctions are operated in a superconductive state.
A superconductive Josephson random access memory in accordance with the invention has subnanosecond access time, cryogenic operation and zero power dissipation in a holding state. The NOR gate assembly in accordance with the invention functions as the row and address decoder of the random access memory which has a highly desirable low power consumption during memory operation.
The superconductive Josephson junction superconductive random access memory of the present invention eliminates the latching logic of prior art superconductive random access memories. The present invention permits a large 1 MB superconductive random access memory to be possible which does not have prohibitive power consumption.
Additionally, logic circuits in accordance with the present invention may be connected with their output circuits in series with the DC power supply which permits current to be recycled from one logic circuit to the next which results in negligible total current consumption. This also eliminates isolation resistors.
The present invention further isolates the logic function from the amplifier output section which both utilize SQUIDs. The resultant separation of logic and output functions facilitates power amplification of the logic output and permits an array of gates to have their outputs powered in series with a single connection to the DC power supply.
While a preferred embodiment of a logic gate assembly in accordance with the invention is a NOR gate, it should be understood that other logic functions may be implemented by the suitable choice of inverters either in the input or outputs.
A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs, each logic input being coupled to a SQUID and each SQUID including a resistance which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUIDs; a DC bias coupled to each SQUID; and an output circuit coupled to each SQUID for providing a logic output in response to the logic inputs. Each logic input is coupled to a transformer through which electrical current flows between the logic input and a reference potential with the transformer coupling the input to the SQUID. Each transformer has a winding within the SQUID and the resistance in each SQUID is preferably at least one resistor coupled to the winding and to Josephson junctions in the SQUID. Each resistor is coupled in a series circuit between the DC bias and the output circuit. The output circuit comprises at least one output SQUID coupled between the DC bias and a reference potential with the at least one output SQUID including an output resistance which eliminates hysteresis in the logic output produced in response to a change in signal level at an input to the at least one output SQUID. Each SQUID is preferably critically damped by the resistance or at least one resistor in responding to a change in signal level at a logic input to the SQUID. The output resistance is preferably a resistor coupled between the DC bias and a reference potential and which provides critical damping in responding to a change in signal level at the input to the output SQUID.
A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs coupled to a logic gate circuit which, in response to logic input signals, provides a logic output signal; a DC bias coupled to the logic gate circuit; and wherein the output circuit includes a logic output which provides the logic output signal, the output circuit including at least one output SQUID coupled between the DC bias and a reference potential with the at least one output SQUID including an output resistance which eliminates hysteresis in the logic output signal produced in responding to a change in the signal level at an input to the at least one output SQUID. The output resistance is preferably at least one resistor coupled between the DC bias and the reference potential and preferably provides critical damping in responding to the change in signal level at the input to the at least one output SQUID.
A superconductive logic gate assembly in accordance with the invention includes a plurality of first logic inputs coupled to a first logic gate circuit and a first output circuit coupled to the first logic gate circuit which, in response to first logic input signals, provides a first logic output signal; a plurality of second logic inputs coupled to a second logic gate and a second output circuit coupled to the
Cho James H.
Tokar Michael
TRW Inc.
Yatsko Michael S.
LandOfFree
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