Superconductive logic gate and random access memory

Details Superconductive logic gate and random access memory Superconductive logic gate and random access memory

1998-11-20

2000-11-28

Tokar, Michael

Electronic digital logic circuitry

Superconductor

326104, 327367, H03K 19195, H03K 1920, H03K 1792

Patent

active

061540447

ABSTRACT:
The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N) each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.

REFERENCES:
patent: 4496854 (1985-01-01), Chi et al.
patent: 5051627 (1991-09-01), Schneier et al.
patent: 5233245 (1993-08-01), Suzuki
patent: 5365476 (1994-11-01), Mukhanov
IEEE Transactions on Applied Superconductivity, vol. 3, No. 1, Mar. 1993, by David A. Feld et al, entitled "A 5-32 Bit Decoder for Application in a Crossbar Switch", pp. 2671-2674.

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