Superconducting read-only memories or programable logic arrays h

Details Superconducting read-only memories or programable logic arrays h Superconducting read-only memories or programable logic arrays h

1983-07-20

1986-12-30

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Superconductive

307462, 307465, 365104, G11C 1144, G11C 1702, H03K 1995

Patent

active

046334394

ABSTRACT:
An A.C. powered type logic array of very high speed operations which employs Josephson devices and which can program any desired logic. The logic array comprises a first logic array which delivers AND logic signals of desired ones of input signals, and a second logic array which delivers OR logic signals of desired ones of the AND outputs. Each of the first and second logic arrays comprises a plurality of bit lines which connect a plurality of arrayed Josephson devices in series at respective rows and each of which has one end connected to a power source and the other end grounded through a resistor, and word lines which are arranged in the column direction of the Josephson device array and which are selectively coupled to the Josephson devices. Whether or not the word lines are coupled to the respective Josephson devices of the arrays, is determined by the patterns of the word lines or the patterns of the Josephson devices, thereby to program the desired logic.

REFERENCES:
patent: 3626391 (1968-07-01), Anacker
patent: 4151605 (1979-04-01), Faris
patent: 4360898 (1982-11-01), Faris
Hamel et al, "High Density Read Only Josephson Device Memory Cell Employing a Single Device", IBM Technical Disclosure Bulletin, vol. 17, No. 11, Apr. 1975, pp. 3349-3350.
Braslau et al, "Josephson Read Only Memory", IBM Technical Disclosure Bulletin, vol 24, No. 1A, Jun. 1981, pp. 277-278.
Broom et al, "Josephson Memory Cell with Magnetic Film", IBM Technical Disclosure Bulletin, vol. 20, No. 7, Dec. 1977, pp. 2839-2840.
Faris et al, "Basic Design of a Josephson Technology Cache Memory", IBM Jour. of Res. Devel., vol. 24, No. 2, Mar. 1980, pp. 143-154.
Terlep, "Personalization Approach for Josephson Array Logic Memory Cells", IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 2059-2060.
Matisoo, "Overview of Josephson Technology Logic and Memory", IBM Journal of Research Development, vol. 24, No. 2, Mar. 1980, pp. 113-129.

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