Supercharge message exchanger

Details Supercharge message exchanger Supercharge message exchanger

2006-08-22

2006-08-22

Nguyen, Tanh Q. (Department: 2182)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S015000, C710S018000, C710S019000, C710S048000, C710S052000, C710S261000, C710S263000, C710S267000

Reexamination Certificate

active

07096296

ABSTRACT:
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

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