Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling
Reexamination Certificate
2006-06-27
2006-06-27
An, Meng-Al T. (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Task management or control
Process scheduling
C712S212000
Reexamination Certificate
active
07069555
ABSTRACT:
Systems and methods perform super-region instruction scheduling that increases the instruction level parallelism for computer programs. A compiler performs data flow analysis and memory interference analysis on the code to determine data dependencies between entities such as registers and memory locations. A region tree is constructed, where the region tree contains a single entry block and a single exit block, with potential intervening blocks representing different control flows through the region. Instructions within blocks are moved to predecessor blocks when there are no dependencies on the instruction to be moved, and when the move results in greater opportunity for instruction level parallelism. Redundant instructions from multiple paths can be merged into a single instruction during the process of scheduling. In addition, if a dependency can be removed the method transforms the instruction into an instruction that can be moved to a block having available resources.
REFERENCES:
patent: 3648253 (1972-03-01), Mullery et al.
patent: 5202993 (1993-04-01), Tarsy et al.
patent: 5430851 (1995-07-01), Hirata et al.
patent: 5438680 (1995-08-01), Sullivan
patent: 6871343 (2005-03-01), Yoshikawa
An Meng-Al T.
Microsoft Corporation
Truong Camquy
Woodcock & Washburn LLP
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