Super pipelined architecture for transmit flow in a network cont

Details Super pipelined architecture for transmit flow in a network cont Super pipelined architecture for transmit flow in a network cont

1995-09-11

1999-08-31

Eng, David Y.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

G06F 1342

Patent

active

059448040

ABSTRACT:
A system and method of pipelining the flow of data in a bus mastered network controller. The concept of successful completion on copy is used. The bus mastering network controller indicates to the CPU that a frame has been successfully transmitted as soon as the data from main memory is copied across system bus to buffer memory in the controller. The driver layer of the network operating system upon receiving the successful completion on copy signal from bus mastering network controller 16 releases its own transmit frame descriptors and buffers associated with the copied frame which enables the lower protocol layer to initiate a new frame transmission while the previous one is still being transmitted. The CPU and bus mastering network controller do not contend for system bus during the setup of the new frame since bus mastering network controller continues transmission from buffer memory. The bus mastering network controller does not wait for a complete indication to transfer the next frame to buffer memory. Rather the next frame is transferred to buffer memory as the previous frame is being transferred to serial side of the controller. This keeps serial side always busy and the data throughput is only limited by the bandwidth capability of the physical link.

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patent: 5485584 (1996-01-01), Hausman et al.
patent: 5563885 (1996-10-01), Witchey

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