Super hybrid SOI CMOS devices

Details Super hybrid SOI CMOS devices Super hybrid SOI CMOS devices

2007-06-05

2009-06-16

Le, Thao X (Department: 4136)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S218000, C438S481000, C438S738000, C438S740000

Reexamination Certificate

active

07547641

ABSTRACT:
The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.

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