Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-09-19
2006-09-19
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S112000, C711S118000, C710S022000
Reexamination Certificate
active
07111134
ABSTRACT:
A subsystem and a subsystem processing method are disclosed in which a storage control unit2000interposed between a plurality of disk units3000and a host computer1000has a nonvolatile cache2400for temporarily holding the read data/write data exchanged between the disk units3000and the host computer1000. The management information for the user data in the cache2400is stored in both the in-cache management information area2420in the cache2400and the in-memory management information area2221in a volatile local memory2210accessible at high speed. Under normal conditions, the management information in the high speed in-memory management information area2221is accessed. At the time of a fault, on the other hand, the management information in the nonvolatile in-cache management information area2420is restored in the in-memory management information area2221, thereby improving the access rate of the cache2400.
REFERENCES:
patent: 5291442 (1994-03-01), Emma et al.
patent: 5437022 (1995-07-01), Beardsley et al.
patent: 5568633 (1996-10-01), Boudou et al.
patent: 5724542 (1998-03-01), Taroda et al.
patent: 6009498 (1999-12-01), Kumasawa et al.
patent: 6233697 (2001-05-01), Yamamoto
patent: 6356978 (2002-03-01), Kobayashi et al.
patent: 6463507 (2002-10-01), Arimilli et al.
patent: 6467029 (2002-10-01), Kitayama
patent: 6763381 (2004-07-01), Kumano et al.
patent: 2002/0023240 (2002-02-01), Yamamoto et al.
patent: 2003/0033496 (2003-02-01), Takagi et al.
patent: 2003/0167375 (2003-09-01), Morishita et al.
patent: 2003/0229757 (2003-12-01), Hosoya et al.
patent: 2004/0221103 (2004-11-01), Morishita et al.
patent: 60-179857 (1985-09-01), None
patent: 03-260851 (1991-11-01), None
patent: 04-273516 (1992-09-01), None
patent: 04-284552 (1992-10-01), None
patent: 08-221215 (1996-08-01), None
patent: 10-222424 (1998-08-01), None
patent: 11-288387 (1999-10-01), None
Ishikawa Atsushi
Tanaka Rie
Bataille Pierre-Michel
Hitachi , Ltd.
Townsend and Townsend / and Crew LLP
LandOfFree
Subsystem and subsystem processing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Subsystem and subsystem processing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Subsystem and subsystem processing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3540807