Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2003-01-14
2004-06-22
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S728000, C257S700000, C257S701000, C257S758000, C257S738000, C257S737000, C257S698000, C257S691000, C361S777000, C361S792000, C361S795000, C174S255000, C174S261000, C174S262000
Reexamination Certificate
active
06753595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a substrate for a semiconductor device and, in particular, to a substrate for a semiconductor device providing electrostatic discharge protection functions.
2. Related Art
Due to the high integrity and the needs of the consuming market, the sizes of semiconductor devices have become more compact. Therefore, many semiconductor package technologies have been developed, such as PGA (Pin Grid Array), BGA (Ball Grid Array), and wafer level packaging.
Among the aforementioned package technologies, the substrate
11
of a BGA semiconductor device
1
(as shown in
FIG. 1
) is used more efficiently to have more bumps
13
. The bumps
13
electrically connect to the pads of the chip
12
via the trace lines and pads of the substrate
11
. Since the number of the bumps is larger, the chip
12
can transmits larger amount of signals via the bumps
13
.
Please refer to
FIG. 2
, the above-mentioned substrate
11
includes a first wiring layer
21
, a ground interconnection-wiring layer
22
, a power interconnection-wiring layer
23
, and a second wiring layer
24
. These four layers are stacked in sequence to form the substrate
11
. The top surface of the first wiring layer
21
is provided with a plurality of first pads
211
for electrically connecting to the pads of the chip
12
. Furthermore, a plurality of first trace lines
212
are formed in the first wiring layer
21
. One end of each of the first trace lines
212
connects to a corresponding first pad
211
.
The ground interconnection-wiring layer
22
and the power interconnection-wiring layer
23
connect to specific pads in the first wiring layer
21
(a ground ring) and specific pads of the second wiring layer
24
(a power ring), respectively, to provide a ground level and a power source level to the chip
12
from external circuits.
The bottom surface of the second wiring layer
24
is provided with a plurality of second pads
241
, each of which is formed with a bump
13
. Moreover, a plurality of second trace lines
242
are formed in the second wiring layer
24
, one end of each of the second trace lines
242
connects to a corresponding second pads
241
. Another end of each of the first trace lines
212
connects to another end of each of the second trace lines
242
via a via hole (not shown in the drawing). The pads of the chip
12
communicate with external circuits through the first pads
211
, the first trace lines
212
, the via holes, the second trace lines
242
, the second pads
241
, and the bumps
13
.
From the above, since the number of second pads
241
of the substrate
11
for connecting to the bumps
13
usually exceeds the number of the pads of the chip
12
, some of the bumps
13
are not electrically connected with pads of the chip
12
. These bumps
13
are called NC Balls. More specifically, the second pads connected with the NC Balls do not connect with the second trace lines, thus the NC Balls do not electrically connected with any pad of the chip
12
. The reason to reserve these NC Balls is to provide input/output terminals requirements when the function of the semiconductor device (such as the BGA semiconductor device
1
mentioned above) is increased. However, when the above-mentioned BGA semiconductor device
1
is under operation, the NC Balls are in a floating status. Under this situation, if an ESD (electrostatic discharge) test is performed on these NC Balls, the electrostatic charges may move into the chip, and then damage other functional pins. If this happens, the functions of the BGA semiconductor device will become abnormal.
Therefore, how to provide a semiconductor device with a superior ESD protection capability has become an important issue to be solved.
SUMMARY OF THE INVENTION
In view of the above, an objective of the invention is to provide a substrate for a semiconductor device with a superior ESD protection capability.
To achieve the above-mentioned objective, the substrate according to the invention includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The top surface of the first wiring layer is provided with a plurality of first pads. The bottom surface of the second wiring layer is provided with a plurality of second pads. The interconnection-wiring layer is provided between the bottom surface of the first wiring layer and the top surface of the second wiring layer. In this invention, at least one of the second pads isn't electrically connected with anyone of the first pads, and other second pads that located adjacent to this second pad, which is not electrically connected with the first pads, electrically connect to the interconnection-wiring layer.
Furthermore, the invention also provides a semiconductor device, which includes the substrate mentioned above and a chip. The chip is provided on the first wiring layer of the substrate, and the pads of the chip are electrically connected with the first pads, respectively.
To sum up, the substrate and the semiconductor device according to the invention provide the level of interconnection-wiring layer to the second pads adjacent to the second pad, which is not connected with the first pads. Therefore, the second pad, which is not connected with the first pads, is shielded and connected with the mentioned NC Ball. As a result, the electrostatic discharge protection capability of a semiconductor device could be improved significantly.
REFERENCES:
patent: 5990547 (1999-11-01), Sharma et al.
patent: 2002/0085334 (2002-07-01), Figueroa et al.
patent: 2002/0139571 (2002-10-01), Mizunashi
patent: 2002/0180015 (2002-12-01), Yamaguchi et al.
patent: 2002/0181185 (2002-12-01), Kabumoto et al.
patent: 04-226097 (1992-08-01), None
patent: 2000-31329 (2000-01-01), None
patent: 2002-217545 (2002-08-01), None
Lin Wei Feng
Lo Wen-Yu
Wu Chung Ju
Yen Wen-Dong
Silicon Integrated Systems Corp
Williams Alexander Oscar
LandOfFree
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