Substrate with gate electrode polysilicon/gate oxide stack cover

Details Substrate with gate electrode polysilicon/gate oxide stack cover Substrate with gate electrode polysilicon/gate oxide stack cover

1997-06-04

1998-09-29

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257410, 257413, H01L 2978

Patent

active

058148639

ABSTRACT:
A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

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patent: 5672525 (1997-09-01), Pan
patent: 5698883 (1997-12-01), Mizuno

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