Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate
2002-06-19
2004-06-15
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With dam or vent for encapsulant
C257S669000, C257S674000
Reexamination Certificate
active
06750533
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to chip carriers, and more particularly, to a substrate for use in a BGA (ball grid array) semiconductor package.
BACKGROUND OF THE INVENTION
A ball grid array (BGA) package is an advanced semiconductor technology characterized by using high-density arrangement of solder balls as input/output (I/O) connections, allowing a chip mounted on a substrate to be electrically connected to an external device by means of the solder balls.
In concern of protecting the chip and bonding wires for electrically connecting the chip to the substrate from external impact and contaminant, a molding process is performed, and the substrate mounted with the chip and bonding wires is placed in a mold cavity, allowing a molding compound to be injected into the mold cavity for encapsulating the chip and bonding wires. As shown in
FIG. 5A
, when a molding compound (as indicated by arrows in the drawing) is injected to a substrate
1
through a gate
10
, bonding wires
11
would be subject to mold flow impact from the molding compound, thereby undesirably causing wire sweep of the bonding wires
11
, especially for those (as circled in the drawing) vertically arranged in position with respect to a flow direction of the molding compound. By virtue of wire sweep, adjacent bonding wires would possibly come into contact with each other, which causes short circuit of bonding wires and adversely affects the yield of package products.
Moreover, as shown in
FIG. 5B
, for the substrate
1
being used in a MCM (multiple chip module) package with a plurality of chips
12
and bonding wires
11
bonded to respective chips
12
being mounted on the substrate
1
, mold flow of the molding compound would be affected by uneven distribution of the chips
12
and bonding wires
11
on the substrate
1
. For example, mold flow would have a higher flowing speed at a region RI free of chips
12
and bonding wires
11
than at a region R
2
mounted with chips
12
and bonding wires
11
on the substrate
1
. Bonding wires
11
(as circled in the drawing) vertically arranged with respect to a flow direction of the molding compound would be directly subject to mold flow impact, thereby causing a greatest extent of wire sweep. Further, uneven flowing speeds of mold flow may also lead to turbulence, making an encapsulant fabricated by the molding compound undesirably formed with voids, which would generate popcorn effect during subsequent high-temperature processes, and thus adversely affect the quality and yield of products.
Accordingly, a plurality of solutions to wire sweep problems are disclosed in the related patents, for example, are U.S. Pat. Nos. 6,031,281, 5,331,205, 6,211,574 and 5,736,792.
As shown in
FIG. 6
, U.S. Pat. No. 6,031,281 teaches forming of a dummy wire
21
at a corner wire-bonding area of a chip
20
. The dummy wire
21
and a functional wire
22
are both bonded to a same single lead
23
, and equally dimensioned in loop height. When the functional wire
22
is subject to mold flow impact and swept, it comes into contact with the dummy wire
21
without causing short circuit, such that other bonding wires
24
can be protected from being touched by the swept wire
22
, and suffer less impact from mold flow of a molding compound. However, forming of the dummy wire
21
would be only effective to certain or restricted-arranged bonding wires e.g. functional wire
22
. For fine-pitch or high-density arrangement of leads or bonding wires, dummy wires would be hardly fabricated to protect functional bonding wires.
U.S. Pat. No. 5,331,205 discloses the use of twice encapsulating processes. As shown in
FIG. 7
, a chip
30
and bonding wires
31
are first encapsulated by a resin material
32
such as epoxy resin-and then-a molding process is performed to form an encapsulant
33
for packaging entire semiconductor structure. However, this method is relatively complex to implement; delamination would easily occur at interface between the resin material
32
and the encapsulant
33
, making quality of fabricated products undesirably deteriorated.
As shown in
FIG. 8
, U.S. Pat. No. 6,211,574 uses a resin material e.g. epoxy resin to form a support member
42
at middle part of bonding wires
41
, so as to hold the bonding wires
41
in position without being swept by mold flow impact during a molding process. However, when the resin material is applied to the bonding wires
41
for forming the support member
42
, it may easily deform the bonding wires
41
or adversely affect electrical connection quality of the bonding wires
41
, thereby reducing the yield of package products.
U.S. Pat. No. 5,736,792 is characterized by applying an epoxy adhesive to bonding wires, for the purpose of firmly positioning the bonding wires without being swept or dislocated; this method leads to the same drawbacks of damaging or affecting electrical connection quality of bonding wires, as described for the above U.S. Pat. No. 6,211,574.
In response to the above drawbacks, how to develop a substrate for use in a semiconductor package so as to prevent wire sweep and short circuit between adjacent bonding wires, is therefore a critical problem to solve.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a substrate with a dam bar structure, allowing mold flow of a molding compound to be impeded by a dam bar and divert its flow direction, so as to effectively reduce the occurrence of wire sweep and short circuit between adjacent bonding wires, thereby preventing voids in an encapsulant and popcorn effect from occurrence.
In accordance with the above and other objectives, the present invention proposes a substrate with a dam bar structure, the substrate being defined on a surface thereof with at least a chip attach area and a wire bonding area surrounding the chip attach area, allowing a chip to be mounted on the chip attach area and electrically connected to the substrate by a plurality of bonding wires bonded to the wire bonding area. A molding gate and a dam bar are formed on the surface of the substrate outside the chip attach area and the wire bonding area, a molding compound is adapted to be injected through the molding gate for encapsulating the chip and the bonding wires, and the dam bar is provided with at least a first gate directed toward the molding gate, a second gate and a third gate opposed to the second gate, wherein the second and third gates are vertically arranged in position with respect to the molding gate, so as to allow the molding compound to be diverted with a flow direction thereof by the dam bar.
By forming of the dam bar on the substrate, the molding compound is adapted to be impeded by the dam bar and diverted to flow through the second and third gates of the dam bar into the chip attach area and the wire bonding area. Moreover, diverted molding compound through the second and third gates flows in a direction substantially parallel to bonding wires arranged nearby the second and third gates; this effectively reduce impact from mold flow of the molding compound to the bonding wires, such that the bonding wires vertically arranged with respect to the molding gate can be effectively prevented from being swept by mold flow impact.
Moreover, after being impeded by the dam bar and divert to flow into the second and third gates, the encapsulating compound would accordingly decrease its flowing speed, which further helps reduce its mold flow impact to the bonding wires, making the bonding wires less likely subject to wire sweep or short circuit. Furthermore, the molding compound would simultaneously flow through the second and third gates to evenly encapsulate the chip and the bonding wires disposed on the chip attach area and the wire bonding area on the substrate respectively.
In another embodiment of the invention, the substrate with a dam bar structure is defined on a surface thereof with a plurality of chip attach areas and wire bonding areas surrounding the chip attach areas respectively, allowing a plurality of chips to
Huang Chien-Ping
Lin Chung-Chi
Wang Yu-Po
Corless Peter F.
Jensen Steven M.
Lewis Monica
Siliconware Precision Industries Co. Ltd.
Zarabian Amir
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