Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-11-29
2004-02-03
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S758000
Reexamination Certificate
active
06686643
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a substrate with at least two metal structures deposited thereon.
Integrated circuits are produced with an ever higher packing density. The consequence of this is that interconnects in metalization planes are at an ever smaller distance from one another. This results in an increase in capacitances which are formed by the interconnects and lead to high signal propagation times, a high power loss and crosstalk. The dielectric used between the interconnects has hitherto mainly been SiO
2
, whose relative permittivity &egr;
r
=3.9.
Methods for lowering the relative permittivity and thus for lowering the capacitance between interconnects are described for example in a reference by B. Shieh et al., titled “Air Gaps Lower k Of Interconnect Dielectrics”, Solid State Technology (February 1999), 51. A first insulating layer made of SiO
2
is produced on a substrate. A metal layer is produced above the insulating layer, and a second insulating layer made of SiO
2
is produced above the metal layer. A photolithographic method is carried out to pattern the second insulating layer and the metal layer in such a way that interconnects are produced from the metal layer. In order to produce cavities between the interconnects, SiO
2
is deposited selectively on the second insulating layer, with the aid of a chemical vapor deposition (CVD) process, until openings between the interconnects are overgrown. SiO
2
is subsequently deposited, with the aid of an HDP-CVD process, in order to prevent the formation of cavities having a very large vertical extent. The cavities adjoin the interconnects, with the result that the dielectric, which determines the capacitance between the interconnects, has a relative permittivity which is almost equal to one. The interconnects are produced by etching the metal layer. However, such a process is disadvantageous particularly when copper is used for the interconnect.
U.S. Pat. No. 5,869,880 shows metalization planes of an integrated semiconductor circuit in which the dielectric between metal structures of a plane has cavities. First, a dielectric is applied on the substrate and the metal structure is disposed in the dielectric. Cavities reaching down to the substrate are then produced in the dielectric. The cavities are subsequently covered with a cover structure.
U.S. Pat. No. 5,949,143 shows a connection structure in which a cavity is formed between adjacent metal lines, the covering layer of which cavity has an indentation in the central region.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a substrate with at least two metal structures deposited thereon, and a method for fabricating it that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which can be produced using a damascene process and form a small capacitance.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor structure containing a substrate, a first insulating layer deposited on the substrate and having cavities formed therein, and a second insulating layer having an upper horizontal surface, composed of a different material than the first insulating layer, and deposited on the first insulating layer. The cavities formed in the first insulating layer are covered by the second insulating layer and are bounded toward the substrate by part of the first insulating layer. At least two metal structures are deposited spaced apart from one another in the first insulating layer and each have an upper horizontal surface lying level with the upper horizontal surface of the second insulating layer. The cavities are created such that they do not adjoin the metal structures and at least one of the cavities is located between the at least two metal structures.
In a damascening process, depressions are produced for the purpose of producing contacts or interconnects in an insulating layer. Afterwards, metal is deposited and planarized by chemical mechanical polishing, with the result that the contacts and the interconnects are produced in the depressions.
A substrate according to the invention has at least two metal structures disposed on it, a first insulating layer being disposed on the substrate. A second insulating layer, which is composed of a different material than the first insulating layer, is deposited on the first insulating layer. Cavities are disposed in the first insulating layer and are covered by the second insulating layer. The metal structures are spaced apart from one another and each has an upper horizontal surface lying level with an upper horizontal surface of the second insulating layer. The cavities are located in such a way that they do not adjoin the metal structures and that at least one cavity is located between the two metal structures. All horizontal cross sections of the cavity in the region of the first insulating layer are essentially identical.
In a method for producing a substrate with at least two metal structures deposited thereon, the first insulating layer is produced on the substrate. The second insulating layer, which is composed of a different material than the first insulating layer, is produced on the first insulating layer. Cavities are produced in the first insulating layer and are covered by the second insulating layer. The metal structures are produced in such a way that they are spaced apart from one another and each have an upper horizontal surface lying level with an upper horizontal surface of the second insulating layer. The cavities are produced in such a way that they do not adjoin the metal structures and that at least one cavity is located between the two metal structures. The cavity is produced in such way that all horizontal cross sections of the cavity in the region of the first insulating layer are essentially identical.
The horizontal cross sections and the horizontal surfaces run essentially parallel to a surface of the substrate on which the first insulating layer is disposed.
The cavity between the metal structures reduces the capacitance formed by the two metal structures.
Since the cavities lie at a greater depth than the metal structures, it is possible to produce the metal structures by producing depressions in the first insulating layer and filling the depressions by depositing metal and subjecting it to chemical mechanical polishing. It is thus possible to use a damascene process for producing the metal structures.
By way of example, the metal structures are contacts or interconnects of a metalization plane of an integrated circuit.
Since the cavities do not adjoin the metal structures, the metal structures can be produced after the production of the cavities, without the cavities being filled with metal when the metal is deposited.
The provision of the second insulating layer makes it possible to produce the cavity in which all horizontal cross sections in the region of the first insulating layer are essentially identical. Therefore, within the first insulating layer, e.g. the cavities do not narrow at the top, which would lead to a larger capacitance.
By way of example, the cavity is produced by a depression being produced in the first insulating layer and being filled with a filling. The second insulating layer is subsequently deposited. In the second insulating layer, an opening is formed over the filling, through which the filling is removed by isotropic etching. The opening is subsequently closed. A further possibility for producing the cavity consists in producing a depression in the first insulating layer and producing at least part of the second insulating layer by selective deposition, in which no material is deposited on the first insulating layer.
A method is described below in which the cavity is produced by selective deposition and in which the cavities and the metal structures are produced next to one another in a self-aligned manner.
A mask is produced on the first insulating layer, which mask covers at le
Gabric Zvonimir
Pamler Werner
Schwarzl Siegfried
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Loke Steven
Owens Douglas W.
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