Substrate via patterns for optimal power distribution and...

Details Substrate via patterns for optimal power distribution and... Substrate via patterns for optimal power distribution and...

2007-05-10

2009-12-29

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

07640523

ABSTRACT:
The embodiments of the present invention provide methods for choosing a via layout pattern(s) for power distribution network in a package for a semiconductor die. The chosen via layout pattern allows the power distribution network to meet the limitation on the loop inductance in order to avoid causing a large ΔV affecting the functionality of semiconductor devices on the die. In addition, the chosen via layout pattern also meets the limitation of total number of vias allowed for the power distribution network in the package.

REFERENCES:
patent: 5877091 (1999-03-01), Kawakami
patent: 6417463 (2002-07-01), Cornelius et al.
patent: 7107561 (2006-09-01), Ali et al.
patent: 2006/0218514 (2006-09-01), Uchida

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