Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-09-24
2002-08-13
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S106000, C438S108000, C029S852000, C174S255000, C174S262000, C174S266000, C174S267000, C361S760000, C361S761000, C361S764000
Reexamination Certificate
active
06432748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a structure of a substrate and to a method of fabricating the substrate with simplified fabrication process in low cost and high reliability. More particularly, the present invention relates to a structure of a substrate where an upper circuit layer and a lower circuit layer are electrically connected by a plurality of blind vias each corresponding to the conducting columns and to a method of fabricating this substrate.
2. Description of Related Art
After several hundreds of processing steps are performed on a chip, integrated circuits with complicated and particular functions are formed on the chip. However, the chip isn't still incorporated into circuits of a printed circuit board (PCB) until a package step for mounting it on a substrate is performed.
FIG. 1
is a schematic, cross-sectional diagram of a conventional IC package. Referring to
FIG. 1
, a substrate
10
, an upper circuit layer
60
a,
a lower circuit layer
60
b,
and a plurality of the plated through holes
50
are provided.
The substrate
10
is made of an insulating material. The upper circuit layer
60
a
is formed on the upper surface of the substrate
10
, and the lower circuit layer
60
b
is formed on the lower surface of the substrate
10
. The upper circuit layer
60
a
is electrically coupled to the lower circuit layer
60
b
by a plurality of the plated through holes
50
which punch through the substrate
10
. Both circuit layers
60
a,
60
b
are covered with a layer of solder mask
70
that electrically isolates the conductive traces from each other and from the environment and contains a number of holes that expose the bonding pads (not shown) of the upper circuit layer
60
a
and the solder pads (not shown) of the lower circuit layer
60
b.
A chip
20
is mounted on the substrate
10
and electrically coupled to the bonding pads of the substrate
10
by the golden wires
40
, while being packaged. The chip
20
and the golden wires
40
are sealed in the packaging material
30
, such as encapsulate. The plural solder balls
80
are attached on the solder pads of the lower circuit layer
60
band then the substrate
10
is incorporated into a printed circuit board (PCB) by said plural solder balls
80
.
Referring to
FIGS. 2A-2D
, a conventional method of fabricating a substrate for semiconductor package comprises the following steps.
(a) An insulating substrate
100
is provided. A plurality of the through holes
105
is formed through the substrate
100
by laser drilling.
(b) The top and the bottom of the substrate and the internal surface of the through holes
105
are respectively plated with copper for forming the copper layers
110
,
120
, and the plated through holes
105
a.
(c) The copper layers
110
,
120
are etched respectively to form an upper and lower circuit layers
110
a,
120
a.
The upper circuit layer
110
a
is electrically conducted to the lower circuit layer
120
a
by the plated through holes
105
a.
(d) The plated through holes
105
a
are plugged with the pastes such as an insulating resin or the conducting epoxy
140
.
(e) The upper and lower circuit layers
110
a,
120
a
of the substrate
100
are covered with a layer of solder mask
150
containing a number of holes that expose defined areas for the bonding pads and the ball pads.
When conventional arts, such as above-mentioned method, are required to form a micro via and a thinner substrate (the thickness is between 0.1 millimeter and 0.04 millimeter), a problem of voids arises. The voids produced during the plugging step are harmful to the reliability test, and it is hard to keep a constant quality.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a method and a structure of fabricating a substrate for integrated circuit package to avoid the occurrence of voids generated in the plugging step in prior art. The etching and plating methods are adapted to an insulating layer and a copper plate for electrically interconnecting the circuit layers, and the plugging step is not required and could be omitted, thus the reliability is enhanced.
Another objective of the present invention is to provide a structure of substrate for integrated circuit package, which comprises an insulating layer, an upper circuit layer, and a lower circuit layer. The circuit layers are formed on the upper and lower surfaces of said insulating layer, and the circuit layers could be electrically connected to each other by a plurality of blind vias each corresponding to the conducting columns embedded into said insulating layer.
To achieve the above-mentioned goal, the present invention offers a fabricating method of a substrate for packaging integrated circuit. The steps are as follows:
(a) A copper plate defined by etching is provided to form the plural conducting columns.
(b) An insulating layer and said copper plate are laminated together, so the conducting columns are embedded into the insulating layer.
(c) Portions of the insulating layer are removed at the defined areas which are located on the conducting columns to form the plural blind vias.
(d) The upper surface of the insulating layer and the plural blind vias are plated with a copper layer.
The copper layer on the surface of the insulating layer and the copper plate are etched for forming an upper and a lower circuit layer.
The upper and lower circuit layers are covered respectively with solder mask layers.
In another variation of the present invention, after the blind vias are plated with copper not fully, the plural solder bumps could be formed on the plural blind vias for attaching a chip.
REFERENCES:
patent: 5989935 (1999-11-01), Abbott
patent: 6228676 (2001-05-01), Glenn et al.
patent: 6261869 (2001-07-01), Radford et al.
Phoenix Precision Technology Corp.
Talbott David L.
Zarneke David A
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