Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
1999-09-30
2001-08-28
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
C250S307000
Reexamination Certificate
active
06281025
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor chips and their fabrication and, more particularly, to post-manufacturing testing of semiconductor chips involving substrate removal.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip-packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or flip-chip packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is flipped over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as Ball Grid Array (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the backside of the chip.
Techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. To acquire these images, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns. For example, on a die that is 725 microns thick, at least 625 microns of silicon is typically removed before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished by first thinning the die across the whole die surface, often referred to as global thinning. Mechanical polishing, such as chemical-mechanical polishing (CMP), is one method for global thinning. Once an area is identified using IR microscopy as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques are often used to thin an area smaller than the die size.
During failure analysis, or for design debug, it is sometimes desirable to make electrical contact and probe certain circuit nodes on the circuit side or front side of a die, or to reconfigure the conductors in an integrated circuit. This access is generally done by milling through substrate to access the node, or milling to the node and subsequently depositing a metal to electrically access the node. Often, global and local thinning as described above are used to accomplish such milling. Accurate determination of the thickness of the silicon in the backside, however, is not readily achieved, making the milling process difficult to control. When not controlled properly, substrate removal can result in damage to or destruction of circuitry and other substrate in the device.
Therefore, it is desirable to have the ability to determine the endpoint of the removal process with sufficient accuracy to avoid milling off the node to which access is being sought, which could often jeopardize further device analysis. It would also be desirable to know how far and at what speed the removal process has proceeded in order to more efficiently and more accurately control the removal process. It would also be useful to develop a method of reaching the endpoint of the die without having to implement the additional steps of global and local thinning of the substrate.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for post-manufacturing analysis of a semiconductor chip device involving the controlled removal of substrate using ion beam energy to mill the substrate and secondary ion detection to automatically stop the milling process when the endpoint is reached or reduce the milling rate when the endpoint is near. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment, the present invention is directed to a method for removing substrate from the backside of a semiconductor chip for post-manufacturing analysis as a function of detected concentration levels of a selected substrate material that is sputtered off of a region of the substrate.
According to another example embodiment of the present invention, there is described a method for removing substrate from a semiconductor chip for post-manufacturing analysis, the chip having a back side opposite circuitry near a circuit side. A portion of substrate in the back side of the semiconductor chip is first removed as a function of the concentration level of a selected substrate material sputtering off of a region of the substrate. An aperture is formed in the substrate as a portion of the substrate is removed. Removal of a selected substrate material from the backside of the chip is detected as the aperture is being formed. Finally, the substrate removal process is controlled as a function of detected concentration levels of the selected substrate material.
In another example embodiment there is described a system for removing substrate from a semiconductor chip having a backside opposite circuitry near a circuit side. The system includes a mechanism for removing substrate from the back side of the semiconductor chip to form an aperture as well as a mechanism for detecting removal of a selected substrate material from the back side of the chip as the aperture is being formed. The system also includes a mechanism for controlling the substrate removing mechanism as a function of detected concentration levels of the selected substrate material.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5821549 (1998-10-01), Talbot et a
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Goruganthu Rama R.
Ring Rosalinda M.
Advanced Micro Devices , Inc.
Christianson Keith
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