Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
1999-09-30
2001-08-21
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Repair or restoration
C438S012000, C438S016000, C438S007000
Reexamination Certificate
active
06277656
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor chips and their fabrication and, more particularly, to semiconductor chips and their manufacture involving substrate removal.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or “flip-chip” packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is “flipped” over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side near the package provides many advantages. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
For flip-chips and other dies requiring or benefiting from back side access, techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for failure analysis of an IC requiring or benefiting from back side access is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the active circuit from the back side of the die using nIR microscopy. Mechanical polishing is one method for global thinning. Using nIR microscopy, an area is identified for accessing to a particular area of the circuit. Local thinning techniques such as laser microchemical etching are used to thin the silicon an area to a level that is thinner than the die size. One method for laser microchemical etching of silicon is accomplished by focusing a laser beam on the back side of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. A specific example silicon-removal process uses the 9850 SiliconEtcher™ tool by Revise, Inc. (Burlington, Mass.) This laser process is suitable for both local and global thinning by scanning the laser over a part of, or the whole, die surface.
During failure analysis, or for design debug, it is sometimes desirable to make electrical contact and probe certain circuit nodes on the circuit side or front side of the die, or to reconfigure the conductors in an integrated circuit. For a flip chip or other die requiring or benefiting from back side access, this would generally involve milling through the back side of the die to access the node, or milling to the node and subsequently depositing a metal on the node. Accurate determination of the thickness of the silicon in the back side, however, is not readily achieved, making the milling process difficult to control. When not controlled properly, milling through the back side can result in destruction of the circuitry that is to be analyzed or debugged.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for removing substrate from a semiconductor chip having a back side opposite circuitry near a circuit side. A portion of substrate in the back side of the semiconductor chip is removed as a function of acoustic energy propagating through the device.
According to another example embodiment of the present invention, a system is configured and arranged to remove substrate from a semiconductor chip having a back side opposite circuitry near a circuit side. An ion bombardment device that is controlled by a controller is used to remove substrate from the back side of the chip. A laser device is used to generate acoustic energy in the chip, and a detection device is configured and arranged to detect the acoustic energy. A computer arrangement is coupled to the detection device and to the controller, and configured and arranged to interpret a detected acoustic energy and to send a signal to the controller responsive to the interpreted acoustic energy.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 4504727 (1985-03-01), Melcher et al.
patent: 5003516 (1991-03-01), Sato et al.
patent: 5196006 (1993-03-01), Klopotek et al.
patent: 5608526 (1997-03-01), Piwonka-Corle et al.
patent: 5633747 (1997-05-01), Nikoonahad
patent: 5748318 (1998-05-01), Maris et al.
patent: 5771094 (1998-06-01), Carter et al.
patent: 5840023 (1998-11-01), Oraevsky et al.
patent: 5959735 (2000-08-01), Maris et al.
patent: 6092422 (2000-07-01), Binnig et al.
patent: 6103539 (2000-08-01), Schaffer et al.
A. Grossman et al., “A new millimeter free electron laser using a relativistic beam with spiraling electrons,” Phys. Fluids 26(1), Jan. 1983, 1983 American Insititute of Physics, pp. 337-343.
S.T. Zavtrak, “Free gas bubbles acoustic laser,” The Institute of Nuclear Problems, Bobruiskaya Str., 11, Minsk 220050, Belarus, 1995 Elsevier Science B.V., A358(1995) pp. 473-474.
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Goruganthu Rama R.
Ring Rosalinda M.
Bowers Charles
Schillinger Laura M.
LandOfFree
Substrate removal as a function of acoustic analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Substrate removal as a function of acoustic analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate removal as a function of acoustic analysis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2517656