Substrate of semiconductor integrated circuit

Details Substrate of semiconductor integrated circuit Substrate of semiconductor integrated circuit

1998-05-27

2003-05-13

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S345000, C257S372000, C257S375000, C257S376000, C257S392000, C257S394000, C257S547000

Reexamination Certificate

active

06563159

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a substrate of a semiconductor integrated circuit, and more particularly to a substrate on which a semiconductor integrated circuit is to be formed, the semiconductor integrated circuit comprising a plurality of circuit sections, each of the circuit sections having a different kind of resistance to which great importance is attached because of different functions of the circuit sections, for example, a circuit section formed by using a plurality of transistors, a circuit section having a lot of storage capacitors of a DRAM formed thereon, and the like.
2. Description of the Background Art
FIG. 45
is a plan view showing a relationship between a wafer and a substrate of a semiconductor integrated circuit. Independent semiconductor integrated circuits are formed on a plurality of regions
2
in a wafer
1
, respectively. Examples of the semiconductor integrated circuit include a semiconductor memory. By taking the semiconductor memory as an example, the prior art related to the substrate of the semiconductor integrated circuit will be described below.
Conventionally, soft error, latch up and electro-static discharge (hereinafter referred to as ESD) have mainly been known as the causes of a malfunction of a memory cell forming the semiconductor memory. In this order, phenomena will briefly be described below. The prior art which has been carried out as countermeasures will be described below.
The soft error means a temporary malfunction which is randomly generated in an integrated circuit due to a passage of &agr;-rays through the integrated circuit and can be recovered. The &agr;-rays are emitted from uranium (U) and thorium (Th) contained in a small quantity in a package housing the integrated circuit, an aluminum wiring to be used for manufacturing the integrated circuit, a silicide electrode, and the like. &agr;-particles are charged to positive bivalence by an atomic nucleus of helium (He
++
). When the &agr;-particle passes through the integrated circuit, an electron-hole pair having a concentration of 10
17
to 10
20
cm
3
is generated. The generated electrons or holes to act as minority carriers flow into a p-type diffusion layer or an n-type diffusion layer to change electric charges stored in the diffusion layer. For this reason, the temporary malfunction, that is, the soft error is caused.
Whether the soft error is actually caused or not greatly depends on how the minority carriers of the generated electron-hole pairs are collected into the diffusion layer in addition to the generation of the electron-hole pairs. As the process of causing the soft error, the following three mechanism are given. Small pieces of a semiconductor on which individual integrated circuits are formed will be hereinafter referred to as substrates.
(1) Drift of the minority carriers in a depletion layer.
(2) Diffusion of the minority carriers on a neutral region in the substrate.
(3) A funneling effect in which an electric field generated by flow of majority carriers accelerates collection of the minority carriers into the diffusion layer.
(1) indicates a mechanism in which the minority carriers generated by &agr;-rays incident on the depletion layer are collected into the diffusion layer by an electric field for drift which is applied to the depletion layer. A time taken for carrier collection is approximately an order of 10
−11
second. On the other hand, there is the Auger process as a carrier recombination process in a silicon substrate which is doped at a high concentration. A lifetime of the minority carrier depends on an impurity concentration of the diffusion layer. The lifetime of the electron ranges from 3×10
−5
second (hole concentration: 10
16
/cm
3
) to 1×10
−9
second (hole concentration: 10
20
/cm
3
). The lifetime of the hole ranges from 1×10
−5
second (electron concentration: 10
16
/cm
3
) to 4×10
−10
second (electron concentration: 10
20
/cm
3
). A time taken for the carrier collection performed by the electric field for drift is approximately an order of 10
−11
second. Therefore, it is apparent that the carrier collection is seldom affected by recombination.
(2) indicates a mechanism in which the minority carriers in the neutral region are collected into the diffusion layer by diffusion. A diffusion coefficient Dn of the electron is 10 to 30 cm
2
/sec. A lifetime &tgr; n of the electron ranges 3×10
−5
to 1×10
−9
second. An average diffusion length 1 d of the electron is given by a square root of a product of the diffusion coefficient Dn and lifetime &tgr; n of the electron.
The average diffusion length 1 d thus obtained ranges from 1 &mgr;m (hole concentration: 10
20
/cm
3
) to 300 &mgr;m (hole concentration: 10
16
/cm
3
). An energy of &agr;-particles emitted from uranium and thorium often ranges from 4 MeV to 5 MeV. A range of the &agr;-particles having an injection energy of 5 MeV is about 23 &mgr;m. Accordingly, if a boron concentration of a p-type substrate is 10
16
/cm
3
, the electrons generated by the &agr;-particles are collected into the diffusion layer by diffusion. If the boron concentration of the p-type substrate is 10
20
/cm
3
, most of the electrons generated by the &agr;-particles in a portion which is deeper than the diffusion layer by 1 &mgr;m or more are recombined and are not collected by the diffusions.
Next, description will be given to the mechanism (3) wherein the minority carriers are collected into the diffusion layer by the funneling effect in which the electric field generated by the flow of the majority carriers accelerates the collection of the minority carriers into the diffusion layer. If the electron-hole pairs generated by the &agr;-particles are separated by the electric field applied into the depletion layer, a dipole electric field is generated by the separated electrons and holes. The dipole electric field weakens the electric field which has been applied into the depletion layer. Therefore, a part of the depletion layer deeply enters the substrate so that a voltage drop is caused. Due to the electric field deeply entering the substrate, the minority carriers generated in the substrate by the &agr;-particles are collected into the diffusion layer formed on a surface of the substrate.
Various well structures have conventionally been proposed in order to prevent the soft error from being caused by the &agr;-particles. A high concentration impurity layer acting as a barrier to the minority carriers has been formed in such a manner that the minority carriers generated in the substrate do not reach the integrated circuit formed in the vicinity of the surface of the substrate of the semiconductor integrated circuit. The high concentration impurity layer has been formed by performing heat treatment after ions are implanted at a high energy. According to this method, a thickness of the impurity layer is insufficient. Therefore, epitaxial wafers such as a p on p
−
wafer, a p on p
+
wafer, a p on p
++
wafer and the like have recently been used as substrate materials. Each of the substrates formed on the epitaxial wafers (which will be hereinafter referred to as a p on p
−
substrate, a p on p
+
substrate and a p on p
++
substrate, respectively) includes a semiconductor surface layer which is subjected to epitaxial growth on a substrate single crystal of the semiconductor cut out of an ingot, and the semiconductor substrates have impurity concentrations of p
−
, p
+
and p
++
. A structure of a substrate of a semiconductor integrated circuit formed by using these wafers will be described below with reference to FIG.
39
.
FIG. 39
is a typical diagram showing a sectional structure of the p on p
−
substrate, the p on p
+
substrate or the p on p
++
substrate according to the prior art. An epitaxial layer
101
which is a p-type semiconductor surface layer is formed on a substr

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