Substrate isolated transistor

Details Substrate isolated transistor Substrate isolated transistor

2002-07-11

2003-03-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Isolation by pn junction only

C438S420000

Reexamination Certificate

active

06537893

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for forming an integrated circuit.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of metal-oxide-semiconductor (“MOS”) transistors, a gate conductor may be arranged upon a gate dielectric, which may be formed upon a substrate. Typically, the gate dielectric is laterally interposed between source and drain regions formed in the substrate, where the source and drain regions may be doped to opposite conductivity type (either n-type or p-type) than the substrate. N-type source/drain regions may be used to form n-channel transistors, and p-type source/drain regions may be used to form p-channel transistors. In complementary MOS (“CMOS”) circuits employing both n-channel and p-channel transistors, n-channel transistors may be formed in p-type “wells” within the substrate, while p-channel transistors may be formed in n-type wells. Such wells may be formed by selectively doping the region of the substrate underlying the subsequently formed gate conductor.
In many instances, electrical isolation between a transistor and an underlying substrate may be beneficial, particularly between a well and a substrate of a CMOS transistor. For example, electrical isolation may be beneficial in non-volatile memory circuits, which use negative voltages for program/erase operations. The electrical isolation between the well and underlying substrate may allow for negative voltages to be used without causing excessive leakage current. In other applications, electrical isolation of integrated circuits that include analog and digital circuit portions, such as mixed signal or mixed mode transistors, may reduce noise coupling between the digital portions and the analog portions. Problems from noise coupling can arise since analog circuit portions tend to be noise-sensitive, while relatively high-power switching transistors, such as output transistors associated with the digital circuit portions, tend to generate noise. In a mixed signal circuit, noise from an output transistor can be coupled to an analog circuit portion through the semiconductor substrate shared by the entire integrated circuit. The severity of this noise coupling problem therefore depends upon how effectively the transistor is isolated from the substrate.
Electrical isolation between a transistor and an underlying substrate may be accomplished by various methods. One approach may include surrounding a circuit well with a material which is dissimilar to that of the substrate, such as a dielectric or a layer of an opposite conductivity type to that of the circuit well. Unfortunately, such a method may require several process steps, thereby increasing overall process time and manufacturing costs. Consequently, production throughput may also be reduced. It would therefore, be desirable to develop a method and a structure, which effectively isolates a transistor from an underlying substrate in a reduced number of process steps.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a device and a method for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate, with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage (e.g. the power supply voltage of the integrated circuit) between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate. Consequently, a method is provided in which to form such an integrated circuit. As such, a method is provided for forming a circuit well over a semiconductor substrate and forming a pair of isolation wells extending along opposite lateral boundaries of the circuit well. In addition, a method of operating such a transistor is provided. In particular, the method may include applying an isolation voltage between the semiconductor substrate and the isolation well surrounding the circuit well to form a single continuous depletion region isolating the circuit well from the underlying substrate.
As stated above, the integrated circuit as recited herein may include a circuit well and a pair of isolation wells. In a preferred embodiment, the circuit well and the isolation wells are adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the isolation wells. For example, the circuit well may be arranged within a semiconductor substrate of the same conductivity type. Preferably, there is no layer of opposite conductivity type formed between the circuit well and the substrate. In addition, the pair of isolation wells may extend along opposite lateral boundaries of the circuit well. In an embodiment, the circuit well may be elongated in one lateral dimension and the pair of isolation wells may extend parallel to the respective lateral dimension. In addition, the pair of isolation wells may form opposite sides of an annular isolation structure. In some embodiments, a dielectric isolation region may be interposed between the circuit well and each of the pair of isolation wells. The isolation wells may be of opposite conductivity type to the circuit well. Furthermore, the carrier concentrations of the circuit well and the isolation wells may be greater than that of the substrate.
The integrated circuit may further include a transistor formed within the circuit well and a contact connected to the circuit well. In one embodiment, the transistor and the contact may be spaced apart along an elongated dimension of the circuit well, such that the contact is not interposed between the transistor and either of the isolation wells. Alternatively or in addition, the integrated circuit may include metallization adapted to connect the isolation voltage between the substrate and the pair of isolation wells. The metallization may be further adapted to connect a well voltage to the circuit well. Such a well voltage may be equal to the voltage level of the voltage applied to the substrate. Alternatively, the well voltage may be above or below the substrate voltage in order to produce a reverse bias across a junction between the circuit well and the isolation wells. In some cases, the reverse bias across the junction between the circuit well and isolation wells may be larger than across a junction between the substrate and the isolation wells. For example, in an embodiment in which the substrate and circuit well are p-type and the pair of isolation wells is n-type, the metallization may be adapted to connect the circuit well to a more negative voltage than the substrate. In addition, the metallization may be further adapted to connect a source of a transistor formed within the circuit well to the well voltage.
A method for forming such an integrated circuit is contemplated herein. The method may include forming a circuit well over a semiconductor substrate of the same conductivity type. Preferably, no layer of opposite conductivity type is formed between the circuit well and the substrate underlying the circuit well. The method may further include forming a pair of isolation wells of opposite conductivity type to that of the circuit well. In particular, the isolation wells may be formed along opposite lateral boundaries of the circuit well. In a preferred embodiment, the circuit well and the isolation wells are adapted such that a single cont

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