Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-09-27
2002-06-11
Kamand, Cuneo (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S777000
Reexamination Certificate
active
06403896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a substrate, and more particularly to a substrate for use in forming a ball grid array (BGA) package.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. To meet the need, the ball grid array (BGA) technology has been developed by the semiconductor industry.
FIG. 1
is a cross sectional view of a typical BGA package
100
according to a preferred embodiment disclosed in U.S. Pat. No. 5,894,410. A semiconductor chip
101
is attached to a die covering area on an upper surface (die attach surface)
102
a
of a substrate
102
with adhesive. Bonding pads (not shown) on the chip
101
are connected with electrically conductive bond wires
103
to a ground ring
102
b
, a power ring
102
c
, and conductive traces
102
d
formed on the upper surface
102
a
of the substrate
102
. Electrically conductive vias (not shown) are formed through the substrate
102
from the ground ring
102
b
, power ring
102
c
, or traces
102
d
on the upper surface
102
a
to a lower surface (mounting surface)
102
e
of the substrate
102
opposite the upper surface
102
a
. The lower surface
102
e
of the substrate
102
is provided with a plurality of solder pads
102
f
electrically connected to the ground ring
102
b
, power ring
102
c
, or corresponding traces
102
d
, respectively. Each solder pad
102
f
is provided with a solder ball
110
for making external electrical connection. The solder balls
110
include power balls for supplying the source voltage, ground balls for supplying the ground potential and signal balls. The ground ring
102
b
, power ring
102
c
, conductive traces
116
and solder pads
118
are usually made of metal with good electrical conductivity such as copper. The chip
101
and a portion of the upper surface
102
a
of the substrate
102
are encapsulated in a package body
120
. Finally, the solder balls
110
are reflowed to attach the package
100
to a mounting board (not shown).
FIG. 2
is a bottom view of the package
100
of FIG.
1
. The solder balls
110
of the package
100
are divided into an outer array and a center array. Typically, the semiconductor chip
101
is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm° C.
−1
and the substrate
102
is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm° C.
−1
. Since there is a significant difference between the semiconductor chip
101
and the substrate
102
in CTE, the semiconductor chip
101
and the substrate
102
expand and contract in different amounts along with temperature fluctuations. It has been found that, the differential thermal expansion between the semiconductor chip
101
and the substrate
102
will significantly increase the chances of failing solder joints in an area which corresponds to the periphery of the semiconductor chip
101
. Therefore, it is desired to locate the solder balls
110
away from the periphery of the semiconductor chip
101
thereby reducing solder failure.
However, during manufacturing processes with rapid temperature increases such as IR reflow, the solder joints close to the periphery of the semiconductor chip
101
are still prone to fail.
The present invention therefore seeks to provide a BGA package which overcomes, or at least reduces the above-mentioned problems of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a BGA package having a substrate with a specific contact pad distribution to enhance solder joint reliability.
The BGA package of the present invention mainly comprises a substrate and a semiconductor chip mounted thereon. The upper surface of the substrate comprises a ground ring. The substrate is characterized in that the lower surface thereof comprises an outer array of contact pads, a center array of contact pads and a plurality of intermediate pads located between the outer array of contact pads and the center array of contact pads, wherein all of the intermediate pads are electrically connected to the ground ring. A plurality of solder balls are attached to the pads of the substrate. The solder balls are typically reflowed to attach the package to a mounting board such as a printed circuit board. The semiconductor chip is electrically coupled to the solder balls by internal routing within the package.
Since the intermediate pads are designed for supplying ground potential, solder failure of some balls attached thereon is not critical. Therefore, the solder balls attached to the intermediate pads helps to absorb stress without sacrificing the reliability of the BGA package.
REFERENCES:
patent: 5598036 (1997-01-01), Ho
patent: 5640047 (1997-06-01), Nakashima
patent: 5703402 (1997-12-01), Chu et al.
patent: 5894410 (1999-04-01), Barrow
patent: 6057596 (2000-05-01), Lin et al.
patent: 6137168 (2000-10-01), Kirkman
patent: 6163071 (2000-12-01), Yamamura
patent: 6201302 (2001-03-01), Tzu
patent: 6242815 (2001-06-01), Hsu et al.
Chiu Chi Tsung
Lee Chang Chi
Ma Shu Jung
Advanced Semiconductor Engineering Inc.
Kamand Cuneo
Norris Jeremy
Stevens Davis Miller & Mosher LLP
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