Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-09-18
2002-09-10
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S784000, C257S786000, C257S697000, C257S690000, C257S692000, C257S734000, C257S738000, C257S737000, C257S774000, C257S698000, C361S794000, C361S777000, C361S780000
Reexamination Certificate
active
06448639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a substrate, and more particularly to a substrate for use in forming a ball grid array (BGA) package.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. To meet the need, the ball grid array (BGA) technology has been developed by the semiconductor industry.
FIG. 1
is a cross-sectional view of a typical BGA package
100
. A semiconductor chip
101
is attached to a die covering area on an upper surface (die attach surface)
102
a
of a substrate
102
with adhesive. Bonding pads (not shown) on the chip
101
are connected with electrically conductive bond wires
103
to a ground ring
102
b
, a power ring
102
c
, and conductive traces
102
d
formed on the upper surface
102
a
of the substrate
102
. Electrically conductive vias (not shown) are formed through the substrate
102
from the ground ring
102
b
, power ring
102
c
, or traces
102
d
on the upper surface
102
a
to a lower surface (mounting surface)
102
e
of the substrate
102
opposite the upper surface
102
a
. The lower surface
102
e
of the substrate
102
is provided with a plurality of solder pads
102
f
electrically connected to the ground ring
102
b
, power ring
102
c
, or corresponding traces
102
d
, respectively. Each solder pad
102
f
is provided with a solder ball
110
for making external electrical connection. The solder balls
110
include power balls for supplying the source voltage, ground balls for supplying the ground potential and signal balls. The ground ring
102
b
, power ring
102
c
, conductive traces
116
and solder pads
118
are usually made of metal with good electrical conductivity such as copper. The chip
101
and a portion of the upper surface
102
a
of the substrate
102
are encapsulated in a package body
120
. Finally, the solder balls
110
are reflowed to attach the package
100
to a mounting board (not shown).
FIG. 2
is a bottom view of the package
100
of FIG.
1
. The solder balls
110
of the package
100
are arranged in a two-dimensional pattern and located away from the package area that is beneath the chip
101
. Typically, the semiconductor chip
101
is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppm° C
−1
and the substrate
102
is usually formed of polymer having a coefficient of thermal expansion of 20-30 ppm° C
−1
. Since there is a significant difference between the semiconductor chip
101
and the substrate
102
in CTE, the semiconductor chip
101
and the substrate
102
expand and contract in different amounts along with temperature fluctuations. Therefore, it is desired to locate the solder balls
110
away from the chip
101
thereby reducing the thermal stresses on the solder joints created by the CTE mismatch between the substrate and the chip. Although effective in reducing solder failure, the outer array pattern has a major disadvantage that all the power balls, ground balls and signal balls are indiscriminately disposed therein. That means the conductive lines for connecting power balls (or ground balls) to the chip on the upper surface of the substrate are long and ineffective. Besides, as the conductive lines become longer, the corresponding impedance, inductance and noise become larger. Larger inductance consumes more power in package and induces power surges in conductive lines and the chip easily. A surge is defined as a high-energy, short-duration voltage, current or power pulse.
Furthermore, the heat generated from the chip during normal operation is dissipated through the solder balls into the mounting board. Therefore, locating the solder balls at the outer perimeter of the package increases the thermal path through the substrate. The longer path increases the thermal impedance of the package and the junction temperature of the chip. It would be desirable provide a BGA package that has a longer product life, lower thermal impedance and better electrical performance than BGA packages of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a BGA package having a substrate with a specific contact pad distribution to obtain better electrical performance and/or thermal performance.
The BGA package of the present invention mainly comprises a substrate and a semiconductor chip mounted thereon. The upper surface of the substrate comprises a die covering area completely covered by the chip, a ground ring and a power ring. The substrate is characterized in that the lower surface thereof comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads. Further, the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring. In another preferred embodiment of the present invention, the lower surface of the substrate is provided with a plurality of dummy pads at a position right under the periphery of the die covering area. In a further preferred embodiment of the present invention, the lower surface of the substrate is provided with a plurality of third contact pads located right under the die covering area wherein there at least exists a certain distance between the third contact pads and the periphery of the die covering area. A plurality of solder balls are attached to the pads of the substrate. The solder balls are typically reflowed to attach the package to a mounting board such as a printed circuit board. The semiconductor chip is electrically coupled to the solder balls by internal routing within the package.
Since the first contact pads are disposed right under the vicinity of the ground ring and the power ring, the conductive lines for connecting the first contact pads to the ground ring and the power ring of the substrate are short and effective thereby obtaining better electrical performance. In other preferred embodiments, the solder balls attached to the dummy pads helps to reinforce and stabilize the bonding between the package and the mounting board thereby enhancing the solder joint reliability therebetween. The solder balls attached to the third contact pads are typically routed directly to ground and/or power pads of the semiconductor chip to provide a direct thermal path from the chip to the mounting board thereby obtaining better thermal performance.
REFERENCES:
patent: 5220490 (1993-06-01), Weigler et al.
patent: 5410107 (1995-04-01), Schaper
patent: 5508556 (1996-04-01), Lin
patent: 5801440 (1998-09-01), Chu et al.
patent: 5818102 (1998-10-01), Rostoker
patent: 5841191 (1998-11-01), Chia et al.
patent: 5864470 (1999-01-01), Shim et al.
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 5894410 (1999-04-01), Barrow
patent: 5903050 (1999-05-01), Thurairajaratnam et al.
patent: 5982632 (1999-11-01), Mosley et al.
patent: 6034427 (2000-03-01), Lan et al.
patent: 6037677 (2000-03-01), Gottschall et al.
patent: 6057596 (2000-05-01), Lin et al.
patent: 6104258 (2000-08-01), Noval
patent: 6137168 (2000-10-01), Kirkman
patent: 6198635 (2001-03-01), Sheney et al.
patent: 6214638 (2001-04-01), Banerjee
patent: 6268238 (2001-07-01), Davidson et al.
patent: 6274925 (2001-08-01), Fazelpour
patent: 6278264 (2001-08-01), Burstein et al.
patent: 2001/0008305 (2001-07-01), McLellan et al.
patent: 6-112319 (1994-04-01), None
Advanced Semiconductor Engineering Inc.
Stevens Davis Miller & Mosher LLP
Williams Alexander O.
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