Substrate for stressed systems and method of making same

Details Substrate for stressed systems and method of making same Substrate for stressed systems and method of making same

2006-12-05

2006-12-05

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

With physical configuration of semiconductor surface to...

C257S618000

Reexamination Certificate

active

07145214

ABSTRACT:
A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

REFERENCES:
patent: 4876219 (1989-10-01), Eshita et al.
patent: 5053835 (1991-10-01), Horikawa et al.
patent: 6121121 (2000-09-01), Koide
patent: 6458622 (2002-10-01), Keser et al.
patent: 6562648 (2003-05-01), Wong et al.
patent: 6570192 (2003-05-01), Davis et al.
patent: 2002/0025652 (2002-02-01), Yanagita et al.
patent: 2003/0129780 (2003-07-01), Auberton-Herve
patent: 2003/0219959 (2003-11-01), Ghyselen et al.
patent: 0 329 400 (1989-08-01), None
patent: 0 331 467 (1989-09-01), None
patent: 1 178 521 (2002-02-01), None
patent: 2 775 121 (1999-08-01), None
patent: 2 787 919 (2000-06-01), None
patent: WO 99/44224 (1999-09-01), None
patent: WO 01/97282 (2001-12-01), None
patent: WO 02/43124 (2002-05-01), None
A.J. Auberton-Hervé et al., “Why Can Smart Cut® Change the Future of Microelectronics?,” International Journal of High-Speed Electronics and Systems, vol. 10, No. 1, pp. 131-146 (2000).
C.P. Chang et al., “A Highly Manufacturable Corner Rounding Solution for 0.18 μm Shallow Trench Isolation,” IDEM, vol. 97, pp. 661-667 (1997).
K. Sakaguchi et al., “ELTRAN® by Splitting Porous SI Layers,” Electrochemical Society Proceedings, vol. 99, No. 3, pp. 117-121 (1999).
Q. Y. Tong et al., Extracts of “Semi-Conductor on Wafer Bonding,” Science and Technology, John Wiley & Sons, Inc., pp. 1-15, 80-99.

Affiliated with

Also associated with

Rating

Substrate for stressed systems and method of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate for stressed systems and method of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate for stressed systems and method of making same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3718452