Substrate for semiconductor package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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C257S701000, C257S780000, C257S730000, C257S784000, C257S787000, C257S690000

Reexamination Certificate

active

06927485

ABSTRACT:
A substrate for a semiconductor package is provided, which includes: a core layer; at least a metal layer applied over each of upper and lower surfaces of the core layer, wherein the metal layer on the upper surface forms a plurality of conductive traces each having a terminal, and the metal layer on the lower surface is defined with a conductive region and a surrounding peripheral region, allowing the conductive region to form a plurality of conductive traces each having a terminal; and an insulating layer applied over each of the metal layers, wherein terminals of the conductive traces and at least a corner portion of the peripheral region are exposed to outside of the insulating layers. During fabrication of semiconductor packages, after a post molding curing process, the vertically-stacked substrates can be easily separated by virtue of a gap being formed between exposed corner portions of the stacked substrates.

REFERENCES:
patent: 5216278 (1993-06-01), Lin et al.
patent: 5640048 (1997-06-01), Selna
patent: 5677575 (1997-10-01), Maeta et al.
patent: 5689091 (1997-11-01), Hamzehdoost et al.
patent: 6111306 (2000-08-01), Kawahara et al.
patent: 6204559 (2001-03-01), Lin et al.

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